Abstract: The present invention relates to a lens-arrayed backlight module, consisting of a housing, a plurality of lamps, and a plurality of lens plates. The lamps are disposed in parallel between the housing and the lens plates to provide illuminating rays. The lens plates correspond to the lamps respectively, each of which being mounted at the center axis of the corresponding lens plate so that the illuminating rays provided by the lamps diffuse through the lens plates. The present invention also provides a liquid crystal display device using the lens-arrayed backlight module.

Abstract: An apparatus for overturning and positioning a cassette is disclosed in the present invention so as to overturn a cassette and position the cassette after overturn. The apparatus for overturning and positioning a cassette comprises a overturning unit mounted on one side of the cassette to overturn the cassette, and at least one movable positioning unit including a base, a positioning member and a rolling member, the movable positioning unit being mounted on one side of the cassette being overturned. The positioning member and the rolling member are mounted on the base. The rolling member projects between the positioning member and the cassette so as to position the overturned cassette in a vertical direction while the positioning member positions the overturned cassette in a horizontal direction.

Abstract: A method for manufacturing a panel of a thin film transistor liquid crystal display device with three mask processes is disclosed. The method includes following steps: forming a transparent conductive layer, a first insulating layer, and a second metal layer on a transparent substrate in sequence; forming a source area, a drain area, a transparent electrode area, and data signal lines through a halftone photolithography and an etching; forming a semiconducting layer and a second insulating layer on the substrate in sequence; forming a semiconducting channel area in a thin film transistor area and contacts on the source area, the drain area, and the data signal lines through a photolithography and an etching; forming a third metal layer and a third insulating layer on the substrate in sequence; forming scanning signal lines and gate lines through a photolithography and an etching.

Abstract: The present invention relates to a liquid crystal display device, which comprises a top polarizer and a lower polarizer, a liquid crystal cell, and a back light assemble, the device is characterized in that the lower polarizer is subjected to an anti-glaring treatment while the top polarizer is not. In the liquid crystal display device (LCD) according to the present invention, since the top polarizer is not subjected to the anti-glaring treatment, the prepared device exhibits a vision property similar to that of cathode ray tube (CRT) display device without brownish nor glittering problems associated with conventional LCD in which a top polarizer is subjected to anti-glaring treatment.

Abstract: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drai

Abstract: A pixel structure on a substrate is provided. The pixel structure includes a scan line, a gate dielectric layer, a data line, a passivation layer, a transparent pixel electrode and a double drain thin film transistor (double drain TFT). The scan line is positioned over the substrate and the gate dielectric layer is positioned over the substrate covering the scan line. The data line is positioned over the gate dielectric layer. The data line extends in a direction different from the scan line. The passivation layer is positioned over the gate dielectric layer covering the data line. The transparent pixel electrode is positioned over the passivation. The double drain TFT is positioned over the substrate in the middle of the pixel structure. The double drain TFT has a gate, a channel layer, a source and two drains. The source and the data line are electrically connected. The two drains are electrically connected to transparent pixel electrode.

Abstract: A method of fabricating a thin film transistor array is provided. A first patterned conductive layer that distributes over an area range exceeding the designated display region is formed over a substrate. A first dielectric layer is formed over the substrate, wherein the first dielectric layer has the thickness getting smaller toward the edge, so that the first patterned conductive layer outside the designated display region is exposed. A second patterned conductive layer is formed over the first dielectric layer. The second patterned conductive layer and the exposed first patterned conductive layer are electrically connected. A second dielectric layer having a plurality of contact openings therein is formed over the substrate. A plurality of pixel electrodes is formed over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings. Finally, various layers outside the designated display regions are removed.

Abstract: Four-mask and three-mask process for TN-type liquid crystal display made with combination of the formation process of the signal line and the formation process of the pixel electrode by forming a signal line of a laminate of a transparent conductive layer and a low-resistance metal layer and a pseudo-pixel electrode, removing a low resistance metal layer on the pseudo-pixel electrode during formation of an opening in a passivation insulating layer to obtain a pixel electrode having a transparent conductive layer. Contact formation process by removing the gate insulating layer during formation of the semiconductor layer, and the formation process of the contact and the formation process of the semiconductor layer, or the formation process of the scan line and the formation process of the contact or the formation process of the scan line and the formation process of the semiconductor layer by introducing half-tone exposure technology.

Abstract: This invention is related to a backlight module for a liquid crystal display device and, more particularly, to a backlight module having a frame with an impact damping design. The impact damping design can damp impact or absorb impact energy, and thereby protect the important components of the backlight module, such as the lamp or the light guide plate. The backlight module includes a light guide plate that has at least one protrusion located at its periphery, and a frame that has at least one indentation part located at its inner side edge. The indentation part engages with the protrusion to fix the light guide plate, and has at least one opening nearby to damp an impact to the indentation part.

Abstract: In the 5-mask and 4-mask processes, during the formation of contacts, breakings in the pixel electrodes and unstable contacts that follow tend to occur. Using source-drain wires consisting of a lamination layer of a heat resistant metal layer and an aluminum layer, the undercuts of the passivation insulating layer formed by removing an aluminum layer in the openings on drain electrodes is resolved by adding manufacturing processes to enlarge the said openings.

Abstract: In the conventional manufacture method that has reduced the number of manufacture processes by forming semiconductor layers and source-drain wires for a channel-etch type insulating gate transistor in a single photo etching process using halftone exposure technology, the channel length increases when the photosensitive resin pattern used at above formation process of source-drain patterning is reduced. Hence the manufacture tolerance (margin) is small, and the yield decreases when the distance between the source wire and drain wire is shortened.

Abstract: When the channel length is shortened in a conventional manufacturing method with a reduced numbers of processes, the manufacturing margin is decreased, causing a lower yield. A four-mask process and a three-mask process proposal are constructed for a TN type liquid crystal display device made by combining a novel technology for streamlining the signal wire formation process and pixel electrode formation process by adopting a half-tone exposure technology, a novel technology for streamlining the electrode terminal protective layer formation process by adopting a half-tone exposure technology in a publicly known source and drain wiring anodization process, and a novel technology for streamlining the scan line formation process and the semiconductor layer formation process, the scan line formation process and the etch stop layer formation process, and the scan line formation process and the contact formation process.

Abstract: A housing for a backlight module is disclosed. The housing has a bottom casing and a side frame for holding a lighting unit, a light guide plate having a protrusion, and optionally a plurality of optical sheets. In particular, an indentation part is formed on the side frame for holding the protrusion, and a slit with unequal width is formed adjacent to the indentation part. A backlight module using the above-mentioned housing is also disclosed therewith.

Abstract: A two TFT pixel structure liquid crystal display includes a first and a second scan line, a first and a second signal line, and a pixel. The pixel includes a pixel electrode and a first and a second transistor. A gate of the first and the second transistor is electrically connected to the first and the second scan line respectively. A source of the first and the second transistor is electrically connected to the first and the second signal line respectively. The drains of the first and the second transistor are electrically connected to the pixel electrode. The ratio of the channel width to the channel length of the first transistor is less than the ratio of the channel width to the channel length of the second transistor.

Abstract: A method of fabricating a thin film transistor array substrate is described. A gate and a scan line electrically connected to the gate are formed on a substrate. A gate insulating layer is formed over the substrate. A patterned channel layer and a patterned ohmic contact layer are formed on the gate insulating layer above the gate. A transparent conductive layer and a metal layer are formed and patterned to define a source/drain region, a data line and a pixel region. A passivation layer exposing the metal layer on the pixel region is formed over the substrate. The metal layer exposed by the passivation layer is removed to expose the transparent conductive layer on the pixel region, using the passivation layer as a photomask, so as to form a pixel electrode. Since the process only needs four photomasks, the process cost can be reduced.

Abstract: A combined frame for housing at least a lamp with one end connected to a power cord is provided. The combined frame comprises a lower frame and an upper frame. The lamp is positioned between the upper frame and the lower frame. The lower frame has an angled cable groove that encloses the power cord from the lamp. One end of the power cord is exposed outside the lower frame. The upper frame is positioned over the lower frame. Through the angled cable groove, the power cord is prevented from sliding in the axial direction of the lamp by any unintended external force and hence pulling power cable away from the lamp. This invention also provides a back light module comprising a light-guiding plate and the aforementioned lamp and combined frame.

Abstract: A frame structure used in a backlight module is disclosed. The frame structure includes an upper frame and a lower frame. By combining the T-shape hook of the upper frame and the corresponding groove of the lower frame, the components of the backlight module, such as the linear light source, the light source fixer, the light guide, the upper diffusing plate, the reflective plate, the lower diffusing plate, and the prism plate can be well assembled. Therefore, an improved positioning and fixing efficacy is provided.

Abstract: An apparatus for inspecting and repairing a circuit defect is disclosed, which has a base; a substrate-supporting platform mounted on the base; a contact inspection module having at least one contact probe and a first driving-system that drives at least one contact probe to contact the circuits formed on the glass substrate and thereby inspect a circuit defect; a non-contact inspection module having at least one non-contact sensor and a second driving-system that drives at least one non-contact sensor to inspect the circuit defect in a non-contact manner; and a laser repair module having a laser head and a third driving-system that drives the laser head to go to the circuit defect and repair the circuit defect. A method for inspecting and repairing a circuit defect is also disclosed therewith.

Abstract: A method for manufacturing a thin film transistor array substrate is disclosed. A first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer are sequentially formed over a substrate, and a first patterning process is carried out to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area. An interlayer insulating layer is formed, and a second patterning process is implemented to form a source/drain contact hole, a scan line contact hole and a terminal contact hole. A transparent conductive layer, a third metal layer and a passivation layer are sequentially formed over the substrate to achieve electrical contacts among above-mentioned contact holes, and a third patterning process is then implemented to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

Abstract: A method for fabricating a TFT having the steps of providing a substrate; sequentially depositing a transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, and a second metal layer on the substrate; performing a first photo-etching-process (PEP) to remove portions of the deposited layers to form a source electrode and a drain electrode and define a channel region, the first PEP includes a first halftone photolithograph process; depositing a second insulating layer and performing a second PEP to form a plurality of contact holes; and depositing a third metal layer and performing a third PEP to remove portions of the third metal layer.