Abstract: Processor elements are described herein. A processor element comprises a silicon layer. The processor element further comprises one or more conductive electrodes. The processor element further comprises dielectric material having a non-uniform thickness, the dielectric material disposed at least between the silicon layer and the one or more conductive electrodes. In use, when a bias potential is applied to one or more of the conductive electrodes, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field profile to induce a quantum dot at an interface between the silicon layer and the dielectric layer. Methods are also described herein.

Abstract: A device for quantum information processing is disclosed herein. According to examples, the device comprises a first plurality of confinement regions for confining spinful charge carriers for use as data qudits. The device further comprises a second plurality of confinement regions for confining spinful charge carriers for use as ancillary qudits, each confinement region of the second plurality of confinement regions couplable to measurement apparatus for measuring an ancillary qudit. The device further comprises a third plurality of confinement regions for confining spinful charge carriers, each confinement region of the third plurality of confinement regions situated between a first confinement region of the first plurality of confinement regions and a second confinement region of the second plurality of confinement regions and for use in mediating interactions between a data qudit of the first confinement region and an ancillary qudit of the second confinement region.

Abstract: Methods are disclosed for controlling charge stability in a device for quantum information processing. According to examples, a device for quantum information processing comprises a first plurality of confinement regions confining spinful charge carriers for use as qudits. The device further comprises a second plurality of confinement regions confining spinful charge carriers, each confinement region of the second plurality of confinement regions adjacent to a confinement region of the first plurality of confinement regions. The device further comprises one or more charge reservoirs, wherein each confinement region of the second plurality of confinement regions is attachable to a charge reservoir.

Abstract: A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively.

Abstract: Processor elements are disclosed herein. A processor element comprises a silicon layer. The processor element further comprises a dielectric layer disposed upon and forming an interface with the silicon layer. The processor element further comprises a conductive via in contact with the dielectric layer, the conductive via comprising a metallic portion having an interface end closest to the dielectric layer and a distal end. A cross-sectional area of the interface end of the metallic portion of the conductive via is less than or equal to 100 nm by 100 nm. In use, the application of a bias potential to the distal end of the conductive via induces a quantum dot at the interface between the dielectric layer and the silicon layer, the quantum dot for confining one or more electrons or holes in the silicon layer. Methods are also described herein.