Abstract: A cost-efficient digital CATV network to improve signal quality, provide reliability, and offer the ability to meet demands for interactive services is described. Analog or digital video downstream channels are converted to a digital format by a digital headend transmitter. Relatively costly error-encoding for digital video channels is also part of the digital headend transmitter. Downstream analog and digital video channels in the digital format are transmitted using time-division multiplex technology from a headend to nodes using standard network protocols, such as SONET. Standard network protocols provide error-monitoring and status indication of transmit data, thus ensuring high signal quality and reliability. Time-division multiplexing facilitates easy adding or dropping of information to a transmit path. Flexibility to add or drop information is critical in providing interactive services. Data from interactive services can be added or dropped at points of presence throughout the digital CATV network.

Abstract: An improved method and system for the determination of jitter buffers enables the generation of buffers having sizes and delays such that, as designed, the buffers capture a substantial majority of packets while not being resource intensive. The present methods and systems provide for improved jitter buffer management by deriving playout buffer adjustments from a plurality of variances, centered around a distribution peak, or mean average delay. The playout buffer monitor uses the buffer adjustments, in size and delay, to select, store and playout packets at their adjusted playout time. The present invention may be employed in a media gateway that enables data communications among heterogenous networks and may be specifically deployed to manage jitter experienced in the course of receiving packetized data and processing the data for further transmission through a packet-based or circuit-switched network.

Abstract: The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks.

Abstract: The present invention is a system on chip having a scalable, distributed processing architecture and memory capabilities through a plurality of parallel processing layers. In one embodiment, the processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (Pus), specially designed for conducting a defined set of processing tasks, are in communication with program memories and data memories.

Abstract: The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.

Abstract: The present invention provides for adaptive filters that have improved computational and memory bandwidth proprieties. When applied to telecommunication applications, the present invention additionally provides for improved methods and systems of canceling echoes. In one embodiment of the adaptive filter of the present invention, a filter, preferably an adaptive finite impulse response (FIR) filter, of an appropriate length, N, is chosen. Once the filter is chosen, convergence is achieved and the filter is converted to an infinite impulse response (IIR) filter. In the course of operation, data is received from an input source and used to adapt the zeroes of the IIR filter using the least means square (LMS) approach, keeping the poles fixed. The adaptation process generates a set of converged filter coefficients that are then applied to the input signal to create a modified signal used to filter the data.

Abstract: The invention is related to methods and apparatus that decode convolutionally encoded data, including trellis-coded modulation (TCM) systems. One embodiment of the invention shares a memory device with a main processor, such as a microprocessor or a DSP, and advantageously relieves the main processor of the relatively time-consuming task of decoding the convolutionally encoded data. This frees up the main processor to execute other tasks. One embodiment of the invention includes a micro-coded state machine that can be programmed to control the decoding of the convolutional codes.