Abstract: A serial interface controller provides for transferring data between a data source having a least one channel and a processor. The serial interface controller has a plurality of control registers; the control registers in turn include a data structure for configuring the serial interface controller for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller; a field for storing the address of the active data channel; and, a field for storing the system clock rate.

Abstract: An analog-to-digital conversion system has an analog-to-digital converter and a digital-filter system. The digital-filter system is connected to the output of the analog-to-digital converter. A processor is connected to the output of the digital-filter system so that the processor transparently receives filtered sample data in the native format of the analog-to-digital converter. An FIR filter circuit in the digital-filter system is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit connected between the analog-to-digital converter and the processor. A configuration and control-register circuit is connected to the circuit for sample collection and data-type conversion, and to the FIR filter circuit, for selectively controlling the operation of the digital filter system according to parameters for data conversion and filter operation passed to the configuration and control-register circuit over a serial interface.

Abstract: A system and method for implementing a digital filter, comprising computing on a digital computer a mathematical model of a digital filter; where the mathematical model has a predetermined first set of parameters. The first set of parameters is converted to a second set of parameters, where the second set of parameters includes control parameters for a pre-selected digital-filter integrated circuit (IC). The system then verifies that the execution of the second set of parameters by the digital-filter IC substantially reproduces the behavior of the mathematical model. The verified second set of parameters is then written to permanent storage on the digital-filter IC. The system preferably reads a device-file map characteristic of the particular filter IC intended to be used to implement the filter under design.

Abstract: We disclose a CIC digital filter having an arbitrary-integer decimation rate. The filter has a shifter connected to its input. The shifter receives a shift control input, where the shift control input is pre-computed as equal to the integer portion of 2 raised to the base-2 logarithm of the gain of the CIC filter. There is a multiplier connected between the input and the shifter. In other embodiments, the multiplier could be connected between the input and the shifter. Sequentially-connected integrator functions are connected to the shifter (or multiplier); a decimation function receives input from the integrator functions; and sequentially-connected differentiator functions receive input from the decimation function. The decimation function has a selectable rate equal to any integer between 1 and a number equal to the predetermined maximum decimation value.