Patents Assigned to Quickshift, Inc.
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Patent number: 7129860Abstract: A parallel decompression system and method that decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. Several devices are described that may include the parallel decompression engine, including intelligent devices, network devices, adapters and other network connection devices, consumer devices, set-top boxes, digital-to-analog and analog-to-digital converters, digital data recording, reading and storage devices, optical data recording, reading and storage devices, solid state storage devices, processors, bus bridges, memory modules, and cache controllers.Type: GrantFiled: March 28, 2001Date of Patent: October 31, 2006Assignee: Quickshift, Inc.Inventors: Manuel J. Alvarez, II, Peter Geiger, Thomas A. Dye
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Managing a codec engine for memory compression/decompression operations using a data movement engine
Patent number: 7089391Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.Type: GrantFiled: August 23, 2002Date of Patent: August 8, 2006Assignee: Quickshift, Inc.Inventors: Peter D. Geiger, Manuel J. Alvarez, II, Thomas A. Dye -
Patent number: 7047382Abstract: A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.Type: GrantFiled: July 26, 2001Date of Patent: May 16, 2006Assignee: Quickshift, Inc.Inventors: Peter Geiger, Manuel J. Alvarez, II, Thomas A. Dye
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Patent number: 7032158Abstract: A method and system for identifying and configuring device-enhanced memory modules at system startup is described. A driver is described that performs a wakeup procedure at startup to identify installed device-enhanced memory modules, detect memory implementations such as interleaving and striping on memory modules, detect error detection and correction (ECC) implementations, and to configure the identified device-enhanced memory modules to use the detected implementations. The method may include several phases including, but not limited to, a start block phase, an ECC configuration phase, an ECC check phase, an interleave detect and configuration phase, a buffer check phase, and a final configuration phase. One or more of the phases may be performed at system startup and/or during normal system operation. Methods for shutting down and providing a sleep mode for device-enhanced memory modules are also described.Type: GrantFiled: April 23, 2001Date of Patent: April 18, 2006Assignee: Quickshift, Inc.Inventors: Manuel J. Alvarez, II, Thomas A. Dye, Peter Geiger
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Patent number: 6885319Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of data compression engines each implementing a different data compression algorithm. A codec system may be designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. Uncompressed data may be compressed using a plurality of compression engines in parallel, with each engine compressing the data using a different lossless data compression algorithm. At least one of the data compression engines may implement a parallel lossless data compression algorithm designed to process stream data at more than a single byte or symbol at one time. The plurality of different versions of compressed data generated by the different compression algorithms may be examined to determine an optimal version of the compressed data according to one or more predetermined criteria. A codec system may be integrated in a processor, a system memory controller or elsewhere within a system.Type: GrantFiled: January 11, 2002Date of Patent: April 26, 2005Assignee: Quickshift, Inc.Inventors: Peter D. Geiger, Manuel J. Alvarez, II, Thomas A. Dye
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Patent number: 6879266Abstract: An memory module including parallel data compression and decompression engines for improved performance. The memory module includes MemoryF/X Technology. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF/X Technology encompasses multiple novel techniques such as: 1) parallel lossless compression/decompression; 2) selectable compression modes such as lossless, lossy or no compression; 3) priority compression mode; 4) data cache techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The parallel compression and decompression algorithm allows high-speed parallel compression and high-speed parallel decompression operation. The memory module-integrated data compression and decompression capabilities remove system bottlenecks and increase performance.Type: GrantFiled: July 14, 2000Date of Patent: April 12, 2005Assignee: Quickshift, Inc.Inventors: Thomas A. Dye, Manuel J. Alvarez, II, Peter Geiger
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Patent number: 6822589Abstract: A parallel decompression system and method which decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. A token may represent one or more compressed symbols or one uncompressed symbol. The parallel decompression engine may also include preliminary select generation logic for generating a plurality of preliminary selects in parallel. A preliminary select may point to an uncompressed symbol in the history window, an uncompressed symbol from a token in the current decompression cycle, or a symbol being decompressed in the current decompression cycle.Type: GrantFiled: January 26, 2000Date of Patent: November 23, 2004Assignee: Quickshift, Inc.Inventors: Thomas A. Dye, Manuel J. Alvarez, II, Peter Geiger
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Patent number: 6819271Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of parallel data compression and/or parallel data decompression engines designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. The plurality of compression/decompression engines may each implement a parallel lossless data compression/decompression algorithm. The codec system may split incoming uncompressed or compressed data up among the plurality of compression/decompression engines. Each of the plurality of compression/decompression engines may compress or decompress a particular part of the data. The codec system may then merge the portions of compressed or uncompressed data output from the plurality of compression/decompression engines. The codec system may implement a method for performing parallel data compression and/or decompression designed to process stream data at more than a single byte or symbol at one time.Type: GrantFiled: January 11, 2002Date of Patent: November 16, 2004Assignee: Quickshift, Inc.Inventors: Peter D. Geiger, Manuel J. Alvarez, II, Thomas A. Dye