Patents Assigned to Quicksilver Technology, Inc.
  • Publication number: 20040093601
    Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.
    Type: Application
    Filed: November 7, 2002
    Publication date: May 13, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Paul L. Master, Eugene Hogenauer, Bicheng William Wu, Dan MingLun Chuang, Bjorn Freeman-Benson
  • Publication number: 20040093479
    Abstract: A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions before the identified instructions and replacing at least one instance of the frequently executed instructions subsequent to the explicit caching instruction with a compressed instruction referencing the index value. One or more instructions can be identified for compression, including groups of consecutive or non-consecutive instructions. The explicit caching instruction directs a node in an adaptive computing machine to store instructions in an instruction storage unit in association with an index value. Instructions stored in the storage unit are retrievable with reference to the index value.
    Type: Application
    Filed: July 24, 2003
    Publication date: May 13, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventor: Amit Ramchandran
  • Publication number: 20040093465
    Abstract: A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.
    Type: Application
    Filed: July 24, 2003
    Publication date: May 13, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventor: Amit Ramchandran
  • Patent number: 6732354
    Abstract: The method, system and tangible medium storing computer readable software of the present invention, provide for program constructs, such as commands, declarations, variables, and statements, which have been developed to describe computations for an adaptive computing architecture, rather than provide instructions to a sequential microprocessor or DSP architecture. The invention includes program constructs that permit a programmer to define data flow graphs in software, to provide for operations to be executed in parallel, and to reference variable states and historical values in a straightforward manner. The preferred method, system, and software also includes mechanisms for efficiently referencing array variables, and enables the programmer to succinctly describe the direct data flow among matrices, nodes, and other configurations of computational elements and computational units forming the adaptive computing architecture.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: May 4, 2004
    Assignee: QuickSilver Technology, Inc.
    Inventors: W. H. Carl Ebeling, Eugene B. Hogenauer
  • Publication number: 20040078403
    Abstract: A reconfigurable filter node including an input data memory adapted to store a plurality of input data values, a filter coefficient memory adapted to store a plurality of filter coefficient values, and a plurality of computational units adapted to simultaneously compute filter data values. Filter data values are the outputs of a filter in response to input data values or a second plurality of filter coefficients to be used in subsequent filter data value computations. First and second input data registers load successive input data values input data memory or from adjacent computational units. Each computational unit comprises a pre-adder adapted to output either the sum two input data values stored in the computational unit or alternately to output a single input data value, and a multiply-and-accumulate unit adapted to multiply the output of the pre-adder by a filter coefficient and accumulate the result.
    Type: Application
    Filed: March 11, 2003
    Publication date: April 22, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: W. James Scheuermann, Otis Lamont Frost
  • Publication number: 20040068716
    Abstract: The invention provides a compiler for generating assembly or configuration instructions from source code for an integrated circuit architecture of a plurality of different IC architectures. The source code is represented as a plurality of nodes of an abstract syntax tree. For each target architecture, a plurality of concrete instruction tiles are generated as concrete classes corresponding to and inheriting from a plurality of function tiles. Each function tile is implemented as an abstract class, represents a corresponding function, such as an ADD or MULT function, and implements a matching operation for the corresponding function. The compiler includes an instruction selector, formed as an abstract class, which implements a matching function and instruction generation for the abstract syntax tree by calling the corresponding matching operations of the concrete instruction tiles, inherited from the plurality of function tiles.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 8, 2004
    Applicant: Quicksilver Technology, Inc.
    Inventor: Cameron Stevens
  • Publication number: 20040054997
    Abstract: Task definitions are used by a task scheduler and prioritizer to allocate task operations to a plurality of processing units. The task definition is an electronic record that specifies resources needed by, and other characteristics of, a task to be executed. Resources include types of processing nodes desired to execute the task, needed amount or rate of processing cycles, amount of memory capacity, number of registers, input/output ports, buffer sizes, etc. Characteristics of a task in clued maximum latency time, frequency of execution of a task, communication ports, and other characteristics. An examplary task definition language and syntax is described that uses constructs including order of attempted scheduling operations, percentage or amount of resources desired by different operations, handling of multiple executable images or modules, overlays, port aliases and other features.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 18, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Ramana Katragadda, Paul Spoltore, Ric Howard
  • Publication number: 20040034602
    Abstract: A method and apparatus for inserting a watermark into a compiled computer program. A location process specifies an insertion point in the compiled program and a watermark generating process inserts a watermark, based on data to be encoded, into the program at the insertion point. The location process is also utilized to specify the location of watermark data to be decoded.
    Type: Application
    Filed: August 16, 2002
    Publication date: February 19, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Owen Rubin, Eric Murray
  • Publication number: 20040034777
    Abstract: A system and apparatus for inserting a watermark into a compiled computer program selectively replaces specified optimizations by non-optimized code to encode bit values of the watermark. The watermark is read by decoding the executable code and assigning the decoded bit values, determined by the presence or absence of optimized code, to bit positions in a signature.
    Type: Application
    Filed: August 16, 2002
    Publication date: February 19, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Eric Murray, Owen Robert Rubin
  • Publication number: 20040028082
    Abstract: A system for efficient sale of devices that comply with licensed standards. A preferred embodiment of the invention uses a generic, or highly adaptable, hardware device. The device can be adapted to adhere to a specific standard, e.g., code-division multiple access, time-division multiple access, etc., after manufacture such as at the point-of-sale to an end user, prior to distribution, or at some other point in a distribution and sales network. This allows manufacturers, retailers and end users to benefit from more competitive selection of standardized communication, data and other formats. Reduction of manufacturing costs and elimination of shipping, or other transfer and storage costs, is also realized.
    Type: Application
    Filed: December 10, 2001
    Publication date: February 12, 2004
    Applicant: Quicksilver Technology, Inc.
    Inventors: Paul L. Master, John Watson
  • Publication number: 20040030736
    Abstract: A computational unit, or node, in an adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric FIR Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad IIR Filter, Radix-2 FFT/IFFT, Radix-2 DCT/IDCT, Golay Correlator, Local Oscillator/Mixer.
    Type: Application
    Filed: May 21, 2003
    Publication date: February 12, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventor: W. James Scheuermann
  • Publication number: 20040025159
    Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.
    Type: Application
    Filed: May 21, 2003
    Publication date: February 5, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Publication number: 20040015971
    Abstract: A method of selecting tasks for execution on a processing node is provided. A plurality of indications of execution times corresponding to a first plurality of tasks is received. Also, a plurality of indications of maximum allowable latencies corresponding to the first plurality of tasks is received. At least a subset of the first plurality of tasks is selected for execution on the processing node based on the plurality of indications of execution times and the plurality of indications of maximum allowable latencies.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 22, 2004
    Applicant: Quicksilver Technology, Inc.
    Inventors: Paul L. Spoltore, Ramana V. Katragadda
  • Publication number: 20040008640
    Abstract: A system for implementing a searcher for use with a communication device is provided. According to one aspect of the system, the searcher includes one or more computational units which are used to perform a PN sequence generation function to generate a sequence of PN codes. The searcher further includes a number of computational units which are used to correlate received signal samples with the PN codes. As each signal sample is received by the communication device, the received signal sample is correlated with a first PN sequence in a parallel manner using the computational units. The correlation results are then accumulated. As the next signal sample is received, this newly received signal sample is similarly correlated with the next PN sequence in a parallel manner. Likewise, the correlation results are accumulated with the previous correlation results. The foregoing process is repeated until all the signal samples needed for correlation are received and correlated with sequences of PN codes.
    Type: Application
    Filed: February 4, 2002
    Publication date: January 15, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Ghobad Heidari, Kuor-Hsin Chang
  • Publication number: 20040010645
    Abstract: A computational unit, or node, in an adaptive computing engine uses a uniform interface to a network to communicate with other nodes and resources. The uniform interface is referred to as a “node wrapper.” The node wrapper includes a hardware task manager (HTM), a data distributor, optional direct memory access (DMA) engine and a data aggregator. The hardware task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The HTM coordinates a nodes assigned tasks using a task lists. A “ready-to-run queue” is implemented as a first-in first-out stack. The HTM uses a top-level finite-state machine (FSM) that communicates with a number of subordinate FSMs to control individual HTM components. The Data Distributor interfaces between the node's input pipeline register and various memories and registers within the node.
    Type: Application
    Filed: May 21, 2003
    Publication date: January 15, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Publication number: 20030227884
    Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals.
    Type: Application
    Filed: December 12, 2001
    Publication date: December 11, 2003
    Applicant: QuickSilver Technology, Inc.
    Inventors: Sharad Sambhwani, Ghobad Heidari
  • Publication number: 20030204638
    Abstract: A method and apparatus for encoding/decoding between interchange format data and structured data utilizes a scripting language. The structure of the data can be controlled by the sequence of commands in the script and changes to the structure can be implemented by changing the script. A parser/interpreter is the only software necessary to implement the technique.
    Type: Application
    Filed: April 29, 2002
    Publication date: October 30, 2003
    Applicant: QuickSilver Technology, Inc.
    Inventor: Eric Murray
  • Publication number: 20030204575
    Abstract: A system for permitting new, or enhanced, functionality to be transferred to an adaptable device. In a preferred embodiment, the permitted functionality is determined according to an accounting method associated with a user's account. This approach allows a user to contract for specific services, functionality, etc. regardless of changes over time such as changes to data formats, communication protocols, external devices or infrastructure, etc. In a preferred embodiment, the functionality is stored on a ubiquitous communications network such as the Internet. Functionality is transferred to different devices as digital information over the network. This allows hardware functionality to be licensed in many forms. For example, site licenses can be obtained for companies; hardware “trialware” can be provided to allow limited functionality for a limited time for lower-cost payments, etc.
    Type: Application
    Filed: April 29, 2002
    Publication date: October 30, 2003
    Applicant: QuickSilver Technology, Inc.
    Inventors: Paul L. Master, John Watson
  • Publication number: 20030200538
    Abstract: The method, system and programming language of the present invention, provide for program constructs, such as commands, declarations, variables, and statements, which have been developed to describe computations for an adaptive computing architecture, rather than provide instructions to a sequential microprocessor or DSP architecture. The invention includes program constructs that permit a programmer to define data flow graphs in software, to provide for operations to be executed in parallel, and to reference variable states and historical values in a straightforward manner. The preferred method, system, and programming language also includes mechanisms for efficiently referencing array variables, and enables the programmer to succinctly describe the direct data flow among matrices, nodes, and other configurations of computational elements and computational units forming the adaptive computing architecture.
    Type: Application
    Filed: April 23, 2002
    Publication date: October 23, 2003
    Applicant: QuickSilver Technology, Inc.
    Inventors: W. H. Carl Ebeling, Eugene B. Hogenauer
  • Patent number: 6618434
    Abstract: The present invention concerns a new type of rake receiver, namely, a multimode rake receiver, which may be included within either a mobile station or a base station, and which has dynamic pilot signal searching and multipath reception and combining capability, for CDMA, cdma2000, W-CDMA, or other mobile communication systems. The adaptive, multimode rake receiver includes a network interface, a plurality of adaptive multimode rake fingers, and a multimode processor. Each adaptive multimode rake finger and the multimode processor are responsive to first configuration information (a first mode signal) to configure for a path reception functional mode and are further responsive to second configuration information (a second mode signal) to configure for a searcher functional mode, providing the multimode rake receiver with acquisition, traffic, and idle modes.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: September 9, 2003
    Assignee: QuickSilver Technology, Inc.
    Inventors: Ghobad Heidari-Bateni, Robert Thomas Plunkett