Abstract: A rotary control input device for a capacitive touch screen is disclosed. The control device comprises a mounting element for retaining the device in place on the capacitive touch screen, a circuit frame rotatably mounted on the mounting element, the circuit frame including a rotation electrode, the rotation electrode being disposed to be adjacent and spaced apart from the capacitive touch screen when the device is retained in place. The device further includes a conductive body portion that is electrically connected to the rotation electrode, the circuit frame being rotatable about the mounting element, with respect to the capacitive touch screen, by a user via the conductive body portion.

Abstract: A button device and a manipulation structure thereof are provided. The manipulation structure includes a plurality of brackets and a plurality of transparent keys respectively fixed to the brackets. Each bracket has an elastic segment, a fixing segment, and a placing segment, the latter two of which are connected to two opposite ends of the elastic segment. Each transparent key includes a press portion and an abutting portion. The press portion is fixed to the fixing segment of the corresponding bracket, and has a touch surface arranged away from the corresponding bracket. The abutting portion extends from the press portion along a displacement direction away from the touch surface, and a width of the abutting portion is less than that of the press portion. The touch surface of each of the transparent keys can be moved along the displacement direction to deform the corresponding bracket by being pressed.

Abstract: The disclosure is related to a method and a system for security verification in a booting process of a computer system. A multi-core processor of the computer system is utilized to perform a security verification operation initiated by a UEFI BIOS. The security verification operation is configured to test if the computer system is qualified as a secure system for a specific use. In one aspect, the multi-core processor architecture has the benefit of providing a more efficient way to allow each of the multiple cores to perform one verification task for one of the peripherals of the system. An embodiment shows that the multiple cores can be individually assigned to perform different tasks such as verifying security of various medium in parallel processes when the computer system is in the booting process.

Abstract: A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset.

Abstract: The disclosure is related to a method and a system for security verification in a booting process of a computer system. A multi-core processor of the computer system is utilized to perform a security verification operation initiated by a UEFI BIOS. The security verification operation is configured to test if the computer system is qualified as a secure system for a specific use. In one aspect, the multi-core processor architecture has the benefit of providing a more efficient way to allow each of the multiple cores to perform one verification task for one of the peripherals of the system. An embodiment shows that the multiple cores can be individually assigned to perform different tasks such as verifying security of various medium in parallel processes when the computer system is in the booting process.

Abstract: Various embodiments of the present invention generally relate to operating an electronic gaming machine to generate a wager-based game. A game control unit and a secure enclosure are provided. The secure enclosure is divided into two compartments. A game control unit including a game controller and two heat dissipation units is disposed within the first compartment. In a second compartment, which is fluidly coupled to the first compartment, fans are provided. The fans drive air from outside the secure enclosure through the heat dissipation units in the first compartment to cool electrical components associated with the game controller which are mounted on an outside of the heat dissipation units. The two heat dissipation units can each include fins and heat pipes. The ends of the fins of the two heat dissipation units can be substantially touching one another to provide a compact form factor.

Abstract: Various embodiments of the present invention generally relate to operating an electronic gaming machine to generate a wager-based game. A game control unit including a secure enclosure are provided. The secure enclosure is divided into two compartments. The first compartment securely contains the game control unit, which includes a game controller used to generate the wager-based game and heat dissipation units. The second compartment includes two fans and is accessed by an easily removable magnetically attached cover. The fans and heat dissipation units provide cooling for electrical components associated with the game controller. The fans can be maintained and replaced without compromising the security of the game controller. This feature reduces costs associated with maintaining the electronic gaming machine.

Abstract: Various embodiments of the present invention generally relate to operating an electronic gaming machine to generate a wager-based game. A game control unit including a secure enclosure are provided. The secure enclosure is divided into two compartments. The first compartment securely contains the game control unit, which includes a game controller used to generate the wager-based game and heat dissipation units. The second compartment includes two fans and is accessed by an easily removable magnetically attached cover. The fans and heat dissipation units provide cooling for electrical components associated with the game controller. The fans can be maintained and replaced without compromising the security of the game controller. This feature reduces costs associated with maintaining the electronic gaming machine.

Abstract: Various embodiments of the present invention generally relate to operating an electronic gaming machine to generate a wager-based game. A game control unit and a secure enclosure are provided. The secure enclosure is divided into two compartments. A game control unit including a game controller and two heat dissipation units is disposed within the first compartment. In a second compartment, which is fluidly coupled to the first compartment, fans are provided. The fans drive air from outside the secure enclosure through the heat dissipation units in the first compartment to cool electrical components associated with the game controller which are mounted on an outside of the heat dissipation units. The two heat dissipation units can each include fins and heat pipes. The ends of the fins of the two heat dissipation units can be substantially touching one another to provide a compact form factor.

Abstract: A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).

Abstract: A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).

Abstract: A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset.

Abstract: A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).

Abstract: A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset.

Abstract: A system for providing write-protection functionality to a memory device includes: a memory device including configurable registers controlling write and erase operations in the memory device; a system interface; a filter logic device in electrical communication with the memory device and further in communication with the system interface; and a power on reset circuit in communication with the system interface and the filter logic device, wherein the power on reset circuit asserts a reset signal to the system interface on startup of the system, further wherein, while the reset signal is asserted to the system interface, the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device and then the power on reset circuit de-asserts the reset signal to the system interface enabling communication between the system interface and the memory device.