Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to methods of mining a block of a distributed ledger. The methods include: receiving a block to be mined, the block including a header hash and a plurality of transactions; creating a first signature based on a first function, where inputs to the first function include the header hash and the plurality of transactions; and creating a second signature based on a second function, where an input to the second function is the first signature. In one example, the second function is a multiplicative inverse function and the method further includes creating the second signature that is a multiplicative inverse value of the first signature with respect to a first irreducible polynomial. The method additionally includes creating a chain of signatures, where each of the signatures is a multiplicative inverse value of a previous output with respect to a respective irreducible polynomial.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.