Patents Assigned to R3 Logic, Inc.
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Patent number: 9275185Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: GrantFiled: January 23, 2014Date of Patent: March 1, 2016Assignee: R3 LOGIC, INC.Inventor: Lisa G. McIlrath
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Publication number: 20140137061Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: ApplicationFiled: January 23, 2014Publication date: May 15, 2014Applicant: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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Patent number: 8464191Abstract: A system and method for identifying circuit components of an integrated circuit includes a processor identifying geometric characteristics of an integrated circuit and sorting the geometric characteristics by order of occurrence of each geometric characteristic. Co-occurring arrangements of the geometric characteristics are then identified and used to identify a standard cell. The geometric characteristics of the standard cell may then be compared to the geometric characteristics of a known cell. Each electrically significant geometric characteristic of the standard cell can be compared to the electrically significant geometric characteristics of the known cell. If the standard cell matches the known cell an instance of the standard cell can be placed in a layout. Once placing the standard cell in the layout a netlist can be extracted.Type: GrantFiled: July 21, 2011Date of Patent: June 11, 2013Assignee: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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Publication number: 20120317528Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: ApplicationFiled: August 14, 2012Publication date: December 13, 2012Applicant: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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Patent number: 8266560Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: GrantFiled: August 26, 2011Date of Patent: September 11, 2012Assignee: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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Patent number: 8209649Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: GrantFiled: August 7, 2009Date of Patent: June 26, 2012Assignee: R3 Logic, IncInventor: Lisa G. McIlrath
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Publication number: 20110314437Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: R3 LOGIC, INC.Inventor: Lisa G. McIlrath
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Patent number: 8032857Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: GrantFiled: September 18, 2008Date of Patent: October 4, 2011Assignee: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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Patent number: 7526739Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: GrantFiled: July 13, 2006Date of Patent: April 28, 2009Assignee: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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High resolution, low power, wide dynamic range imager with embedded pixel processor and DRAM storage
Patent number: 6741198Abstract: A high-resolution, low-power wide-dynamic-range CMOS imager includes an array of pixel imaging cells, each of which embeds with a pixel transducing circuit at the pixel level a digital arithmetic logic processing circuit and a memory circuit. This permits multi-bit analog-to-digital conversion of an electromagnetic sensor output at the pixel level. The processing and memory circuits are usable on a pixel-parallel basis in conjunction with any type of pixel transducing circuit design that produces a binary output. The pixel processing and memory circuits may be configured with pixel transducing circuits in 2-dimensional arrangements on a single substrate or in 3-dimensional arrangements of three layered substrates, and may be used in multiplexed or non-multiplexed fashion with one or several pixel transducing circuits.Type: GrantFiled: June 18, 2002Date of Patent: May 25, 2004Assignee: R3 Logic, Inc.Inventor: Lisa G. McIlrath