Abstract: Disclosed is a frame processing device (10) for processing frames having a plurality of data bits, a plurality of flag bits and a plurality of zero bits inserted within the data bits to avoid there being a pattern of the data bits which coincide with the pattern of flag bits, the frame processing device (10) comprising a host interface (16) for receiving and transmitting said frames having a first data rate, an encryptor (22) and decryptor (28) for encrypting and decrypting the data bits respectively, a network interface (26) for transmitting and receiving encrypted data bits having a second data rate, and an adaptive first-in first out (FIFO) buffers (22 and 30) for compensating for the difference between said first data rate and second data rate.