Abstract: A switched-capacitor analog-to-digital converter implements a conversion scheme involving execution of an algorithmic technique of successive-approximation comprising a number of iterations dependent upon the conversion resolution desired. The algorithm used requires analog processing to produce an output voltage that is two times the output voltage resolved to realize the previous bit. The "times two" function is realized by adding the voltage of the last iteration to itself (i.e., V+V=2V). This is accomplished by storing the output voltage resolved into the previous bit and separately storing a voltage corresponding to that voltage. Both stored voltages are then transferred to an integrator circuit which adds the two voltages and produces the output voltage to be resolved into the next bit.