Abstract: A digital communication apparatus with improved echo suppression includes a circuit for detecting the gain of a far talker signal and a circuit for detecting the gain of a near talker signal. These gains are compared and echo suppression is accomplished by suppressing the lesser of the two gains.

Abstract: Disclosed is a modulation-demodulation system and method for transmitting a plurality of sequentially received information bit sequences, the system including a transmitter having a state machine for expanding by a coding process each information bit sequence into an expanded bit sequence with a coded bit group portion and, in some cases, an uncoded bit group portion. The transmitter further includes a modulator for modulating a carrier signal by one of a plurality of multilevel symbols in a two-dimensional complex plane in response to each sequentially applied expanded bit sequence, with the coded bit group portion being used to specify a subset of the multilevel symbols which when rotated in the complex plane maps upon another subset for each adverse angular rotation and the uncoded bit group portion being used to specify for a selected multiple symbol subset the transmitted multilevel symbol of the carrier signal.

Abstract: In a data communication system involving modems transmitting over a link including terrestrial and one or more satellite links, a nontransmitting modem sends a secondary channel tone during the absence of data transmission. The cessation of said tone is detected by the other modem and used to de-squelch the remote modem receiver. In this manner, the receiver is protected from echoes impinging upon it during long transmission delay times. This method optimizes data throughput by adapting to the transmission delay of the circuit.

Abstract: A secure housing arrangement is provided which requires tools to disassemble. Upper and lower enclosure members (12 and 14) contain latch receiving portions (50) near apertures (44) in the enclosure members. End members (26 and 28) include latching members (42) which resiliently engage with latch receiving portions (50) to form a snap together housing assembly. Disassembly of the housing may be attained by inserting a small tool (72) through small apertures (44) in the housing used to access the latching mechanism. A recessed face plate (30) on the end members (26 and 28) are surrounded by upper and lower lips (38 and 40) which extend outwardly to a point at least flush with the outer-most portion of the upper and lower enclosure members. In this manner, force exerted against the upper and lower lips are substantially absorbed by the end members rather than being transmitted to upper and lower enclosure members.

Abstract: Disclosed is a modulation-demodulation system and method for transmitting a plurality of sequentially received information bit sequences, the system including a transmitter having a state machine for expanding by a coding process each information bit sequence into an expanded bit sequence with a coded bit group portion and, in some cases, an uncoded bit group portion. The transmitter further includes a modulator for modulating a carrier signal by one of a plurality of multilevel symbols in a two-dimensional complex plane in response to each sequentially applied expanded bit sequence, with the coded bit group portion being used to specify a subset of the multilevel symbols which when rotated in the complex plane maps upon another subset for each adverse angular rotation and the uncoded bit group portion being used to specify for a selected multiple symbol subset the transmitted multilevel symbol of the carrier signal.

Abstract: A microprocessor-based video sync generation technique wherein the microprocessor stores a table of transition times and at each time supplies appropriate control signals to a digital-to-analog converter to cause it to generate the desired sync waveform.

Abstract: An automatic adaptive equalizer operative on a test pattern including a carrier-only period, clock-only period and a single test impulse. The equalizer employs a transversal filter under control of a microprocessor. Samples of in-phase and quadrature phase components of the received impulse response are cross correlated and autocorrelated to form elements of a complex matrix equation describing the optimum equalizer tap settings. The microprocessor performs a special interative operation utilizing elements of this equation to rapidly and exactly calculate the optimum initial settings for the tap constants. The clock-only portion of the test pattern is analyzed to accurately set a sampling clock to properly sample the received impulse so that matrix formation can be carried out within the duration of the received impulse. Initial equalization can be achieved in a time on the order of 30 milliseconds at a data rate of 9600 bits per second.

Abstract: The presence of a predetermined pure sinusoidal signal is detected by periodically sampling the actual value of an input electrical signal and, based thereon, predicting what the expected value of the sinusoid would be at a next sampling instant if it is present. The actual and predicted future input signal values are then compared and a running average signal of the thus detected errors in predictions over plural such sampling and prediction cycles are compared to a preset threshold signal value to detect the presence of the predetermined tone. A modem receiver is turned off in the exemplary embodiment when the predetermined test tone is detected to prevent false data or "garbage" being output therefrom.

Abstract: A digital timing recovery circuit operative upon digital samples of the input signal to a data receiver provided at the sample rate to produce a clock correction signal at the symbol rate utilizing a digital periodic filter providing a double restrictive bandpass characteristic about the band edge frequencies and outputting to a nonlinear device followed by a digital sampling filter designed to require only addition and subtraction of the nonlinear device outputs.

Abstract: A digital transmitter wherein a read only memory (ROM) is addressed by subaddresses representing vector components of signal point positions of a desired transmit spectrum. In this manner, greatly reduced ROM storage requirements are achieved.

Abstract: A scrambler/encryption system for randomizing an information-containing data signal for transmission and for reproducing at the receiver the information-containing data signal. The information-containing data to be transmitted is applied to a modulo-two adder, the output of which is the encoded data for transmission and which is also an input of an n stage shift register. An arbitrary logic network, having a plurality of inputs each connected to a plurality of selected shift register stages, produces a particular key signal responsive to the condition of the contents of the selected shift register stages. At the receiver, the received randomized data is fed simultaneously to the input of an n stage shift register and to an input of a modulo-two adder. An identical arbitrary logic network is connected to the receiver shift register and produces the same particular key signal responsive to the same conditions in the shift register. The modulo-two adder in the receiver has as its second input the key signal.

Abstract: A microprocessor-controlled method and apparatus for handling transfer of data in bisynchronous protocol between a data source and a data transmission link. The apparatus responds to particular character sequences to request allocation of transmission capacity from a multiplex controller and to terminate character transmission over the data link. The apparatus includes SIO devices for handling character input and output and a microprocessor and associated memory for examining and queuing the received characters. Bidirectional I/O devices communicating with the microprocessor are used in accomplishing monitoring of interface signal changes and in communicating with the multiplex controller.

Abstract: A system for diagnosing and controlling operation of a plurality of modems, some located at a central site and others at various remote sites. A processor located at the central site selectively addresses microprocessor test and control units at each modem over a secondary channel. The microprocessor test and control units respond to commands to configure and perform various modem tests, operate autonomously to monitor various alarm conditions, and format status reports and alarm maydays for transmission back to the central processor. The system is capable of performing a wide variety of testing, monitoring and network control functions for a very large network of modems.