Abstract: A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

Abstract: An automatic gain control circuit includes a control circuit for controlling a power detector, wherein the control circuit detects a power level change of an input signal and generates a control signal to the power detector so that the power detector can respond to the power level change of the input signal quickly.

Abstract: A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

Abstract: A digital circuit in a baseband receiver to compensate for the IQ mismatch by aligning the amplitude of ? with {tilde over (Q)} and by aligning the phase of {tilde over (Q)} to be 90 degrees away from ?.

Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.

Abstract: A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.

Abstract: An equalizer system includes at least one equalizer configured to equalize an input signal to generate an equalized input signal; a limiting amplifier coupled to the at least one equalizer, and configured to amplify the equalized input signal to a saturated level to generate an output signal; and a control circuit coupled to the at least one equalizer and the limiting amplifier, and configured to generate at least one control signal to the at least one equalizer according to the equalized input signal to adjust a peak gain of the at least one equalizer, wherein the peak gain of the at least one equalizer is at a Nyquist frequency.

Abstract: A circuit with co-matching topology for transmitting and receiving RF signals for return loss improvement, wherein when transmitting RF signals, the LNA is turned off and the capacitance of an adjustable capacitive component is adjusted for transmitting RF signals, and when receiving RF signals, the power amplifier and the adjustable capacitive component are turned off, wherein a matching network is designed in favor of the LNA for receiving RF signals while the adjustable capacitive component can adjust the overall impedance of the circuit including the matching network that is also used when transmitting RF signals and the adjustable capacitive component for improving the transmitting return loss.

Abstract: A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.

Abstract: A single chip for generating multiple differential signals and loop-through signals according to a single-ended RF signal inputted to the single chip, wherein delays between different channels of the multiple differential signals and loop-through signals can be minimized for supporting picture-in-picture applications; in addition, the single chip can integrate a power detector and an AGC circuit for controlling the gain of an LNA inside the single chip, and the gain of the LNA can be outputted from the single chip for different usages.

Abstract: A universal tuning module may include an oscillator, a first tuner configured to process a first television signal, a second tuner configured to process a second television signal, a first switch configured to pass its input containing information associated with an output of the oscillator to said first tuner, and a second switch configured to pass its input containing information associated with the output of the oscillator to the second tuner.

Abstract: An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.

Abstract: The present invention discloses a laser power control system includes a laser diode, a monitor photodiode, a bias control circuit, a modulation control circuit, a digital controller, and a laser diode driver. The laser power control system forms an automatic extinction ratio control loop that is configured to control the extinction ratio of the laser diode by comparing a monitor current with a first target current to keep the extinction ratio of the laser diode at the predetermined first target current. The laser power control system forms an automatic power control loop that is configured to control the average power of the laser diode by comparing the monitor current with the second target current to keep the average power of the laser diode at the predetermined second target current.

Abstract: A circuit with co-matching topology for transmitting and receiving RF signals, said circuit comprising: a first sub-circuit comprising a first inductive component and a first capacitive component to form a low-pass filter for transmitting a first RF signal from a first amplifier to an antenna, wherein the first inductive component is coupled to a ground via a first switch; and a second sub-circuit comprising a second inductive component and a second capacitive component for receiving a second RF signal from the antenna to an input terminal of a second amplifier, wherein said input terminal of the second amplifier is coupled to the ground via a second switch; wherein when the first amplifier is transmitting the first RF signal, the first switch is turned off and the second switch is turned on, and wherein when the second amplifier is receiving the second RF signal, the first switch is turned on and the second switch is turned off.

Abstract: A bias circuit for supplying a bias current to a RF power amplifier by using at least two voltage reference circuits coupled between the base terminal of a bipolar transistor and a voltage supply for generating a bias current to the RF power amplifier, wherein each of the at least two voltage reference circuits respectively clamps to a reference voltage at a corresponding terminal node of the voltage reference circuit on a conductive path having a current flowing from the voltage supply to the base terminal of the bipolar transistor, wherein when the current flowing out of the voltage supply increases, the current flowing through each of the at least two voltage reference circuits will also increases, so that the variation range of the bias current to the RF power amplifier will be kept in a smaller range compared with the variation range of the current flowing out of the power supply, thereby increasing the linearity of the RF power amplifier.

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Abstract: A signal receiver includes a first mixer configured to mix its first input with its second input associated with an oscillating output of a first synthesizer into an output; a first splitter configured to split its input associated with the output of the first mixer into a first output and a second output; a first switch matrix configured to switch its first input associated with the first output of the first splitter into a first output; a second switch matrix configured to switch its first input associated with the second output of the first splitter into a first output; a second mixer configured to mix its first input associated with the first output of the first switch matrix with its second input associated with an oscillating output of a second synthesizer into an output; and a third mixer configured to mix its first input associated with the first output of the second switch matrix with its second input associated with an oscillating output of a third synthesizer into an output.

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: A channel receiving apparatus includes: a first modulating device converts a first channel into a first predetermined frequency according to a first oscillating signal and a second oscillating signal; and a second modulating device converts a second channel into a second predetermined frequency according to a third oscillating signal and a fourth oscillating signal; wherein the first oscillating signal has a first frequency, the second oscillating signal has a second frequency, the third oscillating signal has a third frequency, and the fourth oscillating signal has a fourth frequency, when the third frequency is substantially equal to the first frequency, the third oscillating signal is arranged to be shifted by a predetermined frequency range to have a fifth frequency different from the first frequency, and when the second frequency is substantially equal to the first frequency, the second frequency and the first frequency are shifted by the predetermined frequency range.