Abstract: A structure for facilitating hard disk maintenance comprises a housing, a hard disk bracket, a hard disk backplane, a hard disk, and a hard disk mounting assembly. The hard disk bracket is provided at a front end and a rear end of the housing. The hard disk backplane connects to a bottom of the housing and the hard disk mounting assembly. The hard disk mounting assembly connects to the hard disk bracket. The hard disk backplane is further provided with a hard disk interface, and the hard disk is also connected to the hard disk interface.

Abstract: The present invention is applied to the technical field of solid-state storage, and provided are a solid state disk and a data management method and system. The data management method for a solid state disk comprises: saving the written data in a solid state disk after adding a timestamp to written data; receiving a mark command for marking the data to be invalid, marking an address range corresponding to the invalid data, and saving the marked information in the solid state disk after adding a timestamp to the marked information; comparing the timestamp of the marked information with the timestamp of the data in the marked address range after starting the solid state disk; if the timestamp of the data in the marked address range is earlier than the timestamp of the marked information, marking the address range as invalid, otherwise not marking the address range as invalid.

Abstract: Provided is a method of writing data to a solid-state storage system, wherein the solid-state storage system comprises several logical disks. The method comprises the steps of: from each of the logical disks, allocating at least one idle logic block used for receiving parallel data, wherein each of the logic blocks comprises several logical pages; setting the logical pages with a same page number in respective logic block as one RAID stripe, wherein each RAID stripe is used for storing a set of parallel data and verification information associated with the parallel data; and when data in one of the logical pages is damaged, calculating and restoring the damaged data based on the other data and the associated verification information stored in the RAID stripe where the logical page is located. The present invention also provides a solid-state storage system for implementing the above-mentioned method.

Abstract: The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p?1), m(p?2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p?1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output.

Abstract: A method comprises steps of mapping a same physical page to two mutually coupled logic pages, one logic page being formed by mapping the least significant bit on the physical page, and the other logic page being formed by mapping the most significant bit on the physical page; buffering write data in a buffer memory, and merging the data, which is corresponding to the two mutually coupled logic pages, in the buffer memory into a piece of data corresponding to the physical page according to the mapping relationship between the physical page and the two mutually coupled logic pages; and performing charging/discharging control for the multi-layer memory cell of the physical page according to the merged data, so that a voltage state of the multi-layer memory cell is expressed as a numerical value of the merged data.

Abstract: The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p?1), m(p?2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p?1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output.