Patents Assigned to RAMBU INC.
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Patent number: 12093180Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.Type: GrantFiled: June 29, 2022Date of Patent: September 17, 2024Assignee: Rambus Inc.Inventors: Michael Raymond Miller, Dennis Doidge, Collins Williams
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Patent number: 12086441Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.Type: GrantFiled: August 30, 2021Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Michael Raymond Miller, Steven C. Woo, Thomas Vogelsang
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Patent number: 12087681Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.Type: GrantFiled: July 5, 2023Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Shahram Nikoukary, Jonghyun Cho, Nitin Juneja, Ming Li
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Patent number: 12086060Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.Type: GrantFiled: August 23, 2022Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Taeksang Song, Steven C. Woo, Torsten Partsch
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Patent number: 12086010Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.Type: GrantFiled: August 19, 2022Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Patent number: 12086039Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.Type: GrantFiled: January 13, 2023Date of Patent: September 10, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, J. James Tringali, Ely Tsern
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Patent number: 12079486Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.Type: GrantFiled: June 22, 2023Date of Patent: September 3, 2024Assignee: Rambus Inc.Inventors: Aws Shallal, Micheal Miller, Stephen Horn
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Patent number: 12079135Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.Type: GrantFiled: June 14, 2023Date of Patent: September 3, 2024Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 12074623Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: GrantFiled: May 8, 2023Date of Patent: August 27, 2024Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Yikui Jen Dong, Arash Zargaran-Yazd, Wendemagegnehu Beyene
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Patent number: 12072802Abstract: A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.Type: GrantFiled: January 10, 2023Date of Patent: August 27, 2024Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 12073111Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.Type: GrantFiled: September 8, 2022Date of Patent: August 27, 2024Assignee: Rambus Inc.Inventors: Michael Raymond Miller, Dongyun Lee
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Patent number: 12072817Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.Type: GrantFiled: June 29, 2023Date of Patent: August 27, 2024Assignee: Rambus Inc.Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
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Patent number: 12067261Abstract: A serial presence detect (SPD) device includes a region of nonvolatile memory for SPD data and an additional region for other (e.g., vendor) use. The additional region may be subdivided into write protect regions that can be individually and independently write protected. To configure the write protection, a password key scheme is used to enter a mode whereby the write protection attributes may be configured. Another password key scheme is used to exit the write protection configuration mode.Type: GrantFiled: July 5, 2022Date of Patent: August 20, 2024Assignee: Rambus Inc.Inventors: Aws Shallal, Chen Chen
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Patent number: 12067294Abstract: Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.Type: GrantFiled: June 6, 2022Date of Patent: August 20, 2024Assignee: Rambus Inc.Inventor: Dongyun Lee
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Patent number: 12067285Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.Type: GrantFiled: January 4, 2023Date of Patent: August 20, 2024Assignee: Rambus Inc.Inventor: Scott C. Best
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Patent number: 12066957Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.Type: GrantFiled: April 3, 2023Date of Patent: August 20, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, Kenneth L. Wright
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Patent number: 12062413Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.Type: GrantFiled: August 15, 2023Date of Patent: August 13, 2024Assignee: Rambus Inc.Inventors: Andrew M. Fuller, Robert E. Palmer, Thomas J. Giovannini, Michael D. Bucher, Thoai Thai Le
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Patent number: 12050787Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.Type: GrantFiled: February 10, 2022Date of Patent: July 30, 2024Assignee: Rambus Inc.Inventors: Shih-ho Wu, Christopher Haywood
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Patent number: 12050513Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.Type: GrantFiled: April 25, 2023Date of Patent: July 30, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, John E. Linstadt, Liji Gopalakrishnan
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Patent number: 12040035Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.Type: GrantFiled: August 11, 2023Date of Patent: July 16, 2024Assignee: Rambus Inc.Inventors: Scott C. Best, John Eric Linstadt, Paul William Roukema