Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.