Patents Assigned to RamTek Technology, Inc.
  • Patent number: 7221147
    Abstract: A method for testing a ball grid array package includes the following steps. Firstly, a printed circuit board having a plurality of contact pads thereon is provided. Then, a ball grid array test socket assembly having a connecting interface, a plurality of resilient contact members and a plurality of conducting members penetrating through the connecting interface is provided. The first terminal of each conducting member is in contact with the second terminal of corresponding resilient contact member. The second terminal of each conducting member is in contact with corresponding contact pad on the printed circuit board. Afterwards, the ball contacts of the ball grid array package are in contact with corresponding first terminals of the resilient contact members so as to test the ball grid array package.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: May 22, 2007
    Assignee: RamTek Technology Inc.
    Inventors: Cheng Hsun Tsai, Chen Lien Chiang
  • Publication number: 20060261837
    Abstract: A method for testing a ball grid array package includes the following steps. Firstly, a printed circuit board having a plurality of contact pads thereon is provided. Then, a ball grid array test socket assembly having a connecting interface, a plurality of resilient contact members and a plurality of conducting members penetrating through the connecting interface is provided. The first terminal of each conducting member is in contact with the second terminal of corresponding resilient contact member. The second terminal of each conducting member is in contact with corresponding contact pad on the printed circuit board. Afterwards, the ball contacts of the ball grid array package are in contact with corresponding first terminals of the resilient contact members so as to test the ball grid array package.
    Type: Application
    Filed: January 23, 2006
    Publication date: November 23, 2006
    Applicant: RamTek Technology Inc.
    Inventors: Cheng Tsai, Chen Chiang
  • Patent number: 6900530
    Abstract: A stacked IC includes a first IC package unit, a second IC package unit and an interface layer. The first IC package unit includes an IC chip, an encapsulant resin and a plurality of lead wires. The IC chip is encapsulated by the encapsulant resin. Each of the lead wires includes a first end connected to the IC chip and encapsulated by the encapsulant resin, a second end extending outside the encapsulant resin, and a bend portion arranged between the first end and the second end and having at least one surface exposed outside of the encapsulant resin. The second IC package unit has the same structure as the first IC package unit. The interface layer is sandwiched between the first IC package unit and the second IC package unit, and has a first side connected to the bend portion of the first IC package unit and a second side connected to the second end of the second IC package unit.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 31, 2005
    Assignee: RamTek Technology, Inc.
    Inventor: Cheng-Hsun Tsai