Abstract: A higher order language-directed computer architecture particularly adaptable for fourth generation program languages. The computer includes a memory which stores package modules and task modules for programs, each of which includes a control segment representing control for the module, a code segment representing instructions for the computer relating to the module, a data segment, a type segment representing type descriptors declared for the module, a queue segment containing synchronization messages for controlling queuing between task modules and an import segment containing lists of objects outside a module which are accessible within the module. The computer simultaneously manipulates portions of the segments based on instructions in the code segment.

Abstract: A bus apparatus for interconnecting a plurality of nodes is disclosed. The nodes may comprise processors, input/output subsystems, or the like. Each node maintains a unique priority number; the priority numbers are determined independently by each node. Separate updating of the priority numbers occurs for acknowledgement packets as compared to data transmissions. This provides for quick, efficient acknowledgement of transmissions and does not unfairly penalize a popular receiving node. Two different interface circuits are described, one particularly suitable for use with an input/output subsystem, and the other for a processor.

Abstract: A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which selects a number of set locations in the main memory. Simultaneously, a portion of the address field is fed to a set association logic circuit for parallel processing. The set association circuit contains tag storage memories and comparators which store tag values. These values are compared with address fields, and if a match occurs, one of the comparators selects a 128-bit word from the main memory. A hash function is also used to provide for dispersal of storage locations to reduce the number of collisions of frequently used addresses. Because of hardware implementation of hashing and least recently used (LRU) algorithm, a constant predetermined cycle time is realized since all accessing functions occur substantially in parallel.