Abstract: A word wise search is performed on an MPEG-2 stream. For every word, the invention finds word-aligned patterns of 0×00 0×00 or 0×00 0×01. The algorithm applied by the invention examines the input stream buffer for the first word aligned 0 in which further testing determines is the first byte of a valid start code, and sets the sub-buffer defined by the start of the search to the location of this discovered start-code as the zero-word reach. A second search is performed in the same part of the input stream buffer, this time looking for word aligned 1's (i.e. byte pattern 0×00 0×01). For each word aligned 1 that is a start code, an entry is made into a start code list. When all of these have been found, the offset of the start code ending the current zero-word reach is added to the list of start-code offsets. This process is repeated from the 0 word reach until the end of the buffer is encountered.

Abstract: A method and apparatus for optimal handling of high bandwidth streaming data in a computer system minimizes computational activities to achieve maximal performance. This performance improvement is accomplished by minimizing the amount of memory copying and also by minimizing the number of allocation and deallocations of objects which occur. Memory copying is a CPU/bandwidth intense operation when there is high speed streaming data on the input. The allocation and deallocation of objects is a system resource intense activity and requires a very significant amount of CPU processing per invocation in a computing device. Using a combination of techniques, the invention provides a technique that reduces both the number of memory copies as well as the number of objects which get allocated and deallocated during the course of operating on the streaming media data.

Abstract: A digital input switching audio power amplifier uses a simple logic circuit and/or software program for signal processing and, therefore, does not require an expensive DSP processor. The invention provides an approach that allows the integration of power level meters and volume controls in the logic circuit. In one embodiment of the invention, the amplifier accepts multiple inputs, an active one of which may be digitally selected. The invention uses this novel approach to signal processing to achieve high performance. The invention also provides lower system cost as a result of the higher levels of system integration provided by the logic circuit. Increased system versatility results from a modular design which allows the production of an amplifier having optimum cost-to-performance ratios. The amplifier is implemented in ASIC and FPGA circuitry, such that a designer using the invention is provided with flexibility in choosing the various operating parameters of the amplifier, e.g.