Abstract: The versatility provided by network nodes in accordance with the present invention allows the formation of networks using different types of links, links with differing bandwidth, data rates, and bit error rates, as well as both asymmetric and symmetric links. For example, a network can include a first network node coupled to a second network node with a wireless link. The network can include a third network node coupled to the second network node an optical link and coupled to the first network node by a wireless link. A fourth network node can be easily inserted between the third network node and the third network node using wireless links. The optical link between the second and third network nodes can operate at one bandwidth and the various wireless links would operate at other bandwidths depending on the environmental conditions between each pair of nodes.

Abstract: A high-speed optical network includes according to the invention a housing having a plurality of slots for accommodating a number of line cards and an optional backplane facilitating communication between the line cards. The line cards include a client communication interface and a DWDM communication interface, for example, gigabit Ethernet interface, SONET interface or DWDM interface. Advantages of the invention include a high-speed network and network components that are capable of performing at a level consistent with optical network systems and which efficiently supports DWDM in a space-effective and cost-effective manner.

Abstract: To provide the quality and reliability of a fiber optic link over a wireless link, network nodes in accordance with the present invention include a link quality management unit, which controls multiple transmission parameters of a wireless interface in response variable link conditions. For example, the link quality management unit of one embodiment of the present invention controls transmission power, modulation, and error correction. In general, a receiving network node provides feedback to a transmitting network node. Thus, in many embodiments of the present invention, the link quality management unit includes a signal quality detector, which measures a signal quality value, such as bit error rate, signal to noise ratio, or error vector magnitude. The measured signal quality is transmitted back to the transmitting node so that appropriate changes can be made to the transmission parameters.

Abstract: A high-speed optical network includes according to the invention a housing having a plurality of slots for accommodating a number of line cards and an optional backplane facilitating communication between the line cards. The line cards include a client communication interface and a DWDM communication interface, for example, gigabit Ethernet interface, SONET interface or DWDM interface. Advantages of the invention include a high-speed network and network components that are capable of performing at a level consistent with optical network systems and which efficiently supports DWDM in a space-effective and cost-effective manner.

Abstract: A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.

Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.

Abstract: A method of efficiently coordinating the communication of data and commands between multiple entities in a system is disclosed. A transaction protocol enabling centralized scheduling of chains of data transfers in a system is disclosed.

Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.

Abstract: The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.

Abstract: A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.

Abstract: Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Three iterations produce a result with accuracy sufficient for computer graphic applications. The initial estimate and input operand are scaled to minimize final adjustments to the result mantissa and final exponent adjustments required by the algorithm are performed concurrently with any adjustment required by rounding. A pipelined implementation of the algorithm produces a result with a latency of 24 and a repeat rate of 21 clock cycles.

Abstract: The invention relates to the field of system on a chip, SoC, information processing architecture and particularly to the use of a homogenous, concurrent-communication interconnection architecture that allows a variety of different functions to be connected together and their full synergistic performance realized. The functions are decoupled from each other, allowing performance optimization of each function without regard for the other functions on the chip. The system data flow is coordinated using a overall system schedule allowing data interactions to be orchestrated efficiently.

Abstract: Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.

Abstract: In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.

Abstract: A method and system for high speed bussing in microprocessors and microelectronic devices is disclosed. The method and system implement a type of differential bus with distributed bus pre-charge units designed to decrease bus pre-charge time. The method and system utilize a universal self-tracking clock signal to determine the minimum required bus pre-charge time. The time saved by decreasing the bus pre-charge time can be directly applied to the bus evaluation period thereby increasing system performance and reliability.