Abstract: A comparator circuit for operation at video rate signals includes input switches to alternately couple a reference and a signal potential to a summing capacitor. The capacitor is coupled to the input of a first inverting amplifier. The amplifier includes a switch between input and output terminals for selectively autozeroing the amplifier. The amplifier is direct coupled to the input of a second inverting amplifier having an autozero circuit exclusive of a connection to the input of the second amplifier. Timing circuitry for controlling the autozero function is arranged to minimize the effects of clocking transients upsetting the autozeroed potentials thereby reducing the response time and enhancing the sensitivity of the comparator.
Abstract: A method of forming a variable width channel in a body comprises the steps of forming a surface grating having a photoresist layer thereon. The photoresist layer has a plurality of depressions and a planar photomask is then positioned over the photoresist layer. The photoresist layer is subsequently exposed and developed and due to the divergence of light into the depressions covered by the photomask, forms a variable width opening. A portion of the body exposed in the opening is removed to form a channel with a sidewall having a surface contour corresponding to an edge of the opening.
Abstract: The effective capacitance of the floating diffusion in a floating-diffusion electrometer is modified to adjust electrometer sensitivity. This is done by changing the direct potential applied to a gate electrode proximate to the floating diffusion.
Abstract: A method of polishing a roof-shaped, or bevelled, tip having a predetermined angle on the end of an optical fiber is disclosed. The method comprises placing an optical fiber in contact with an abrasive tape at an angle corresponding to the desired predetermined angle. The fiber is moved towards the tape beyond the point of contact so as to cause a bend in the fiber. Upon moving the abrasive tape, the compliance of the fiber, by virtue of the bend, provides a pressure of the fiber against the tape to enable polishing to occur. As polishing continues the pressure decreases until enough material is removed so as to eliminate the bend and impart the predetermined angle to the fiber tip. The fiber may be rotated to polish the other side in a similar manner, if so desired.
Abstract: A switch-mode power supply includes the series combination of an inductor and a controllable switch adapted to be coupled to a voltage source for producing a succession of increasing and decreasing ramp currents through the inductor. The average value of the ramp currents is controlled by a feedback loop. A second controllable switch arrangement is coupled for causing the current leaving the inductor to recirculate through the inductor during those intervals in which the second switch is conductive. An integrator is coupled to the inductor for integrating ramp current from the inductor during those intervals in which the second switch is nonconductive, for generating load voltage. A second feedback arrangement senses the load voltage and controls the average conduction of the second switch to control the load voltage. In one embodiment, an inverter receives ramp current from the inductor and generates alternating current, which are transformed and rectified before application to the integrator.
Abstract: A leadless ceramic chip carrier (LCCC) is soldered to mating conductor pads on a circuit board by depositing a layer of solder paste on peripheral contact pads and on an array of central pads on the board. The same solder paste type and melt temperature are used for both peripheral and central pads. the contact pads of the LCCC are placed on the solder layers and the assembly exposed to infrared radiation from above or other energy source. The LCCC body shades the solder on the central pads resulting in the solder layers at the peripheral pads melting first. The solder on the central pads then melts and balls up due to surface tension lifting the LCCC away from the board stretching the melted solder at the peripheral pads which make the electrical connections to the LCCC contacts.
Abstract: A radio frequency transmitter simultaneously transmits both a local oscillator frequency and that frequency modulated by an information content signal. A receiver receives a carrier wave that is at the opposite edge of a channel from that of the local oscillator. The transmitted and received information signals can be of opposite type sidebands.
Abstract: A waveguide bandpass filter includes a fenestrated conductive septum which may be printed on a dielectric circuit board. The center frequency is tuned by a dielectric plate parallel with the septum and contiguous with the fenestrations which is movable in a direction orthogonal to the septum.
Abstract: A device header with a multilayer coating overlying its entire surface, and a method of making said header, are disclosed. The multilayer coating comprises an electrolytic nickel layer and a gold layer in the device mounting area of the header, whereas the rest of the header is coated with electroless nickel, a first gold layer, electrolytic nickel, and a second gold layer. In the fabrication, the electroless nickel layer is deposited over the entire header followed by the first gold layer. Upon removing these layers from the device mounting area, the first gold layer remaining on the rest of the header acts as a mask for the etching of the mounting area preparatory to deposition of electrolytic nickel and the second gold layer. The header has the advantage of the excellent coverage of electroless nickel over most of its surface, but with the advantage of high purity electrolytic nickel in the device mounting area.
October 15, 1987
Date of Patent:
July 26, 1988
Frank J. Fuccello, Sr., Frank Z. Hawrylo, Robert E. Harwood
Abstract: An adaptive interference cancelling signal processing system includes N+1 processors for cancelling N interfering auxiliary signals from a primary signal. During a prelook or inactive period of the primary signal when a component of interest is not present in the primary signal, the N+1 processors are configured to produce the N(N+1)/2 correlation coefficients L.sub.ij which enable weights for the auxiliary signals to be determined. The same N+1 processors may be reconfigured to convert these L.sub.ij values to the N weights without requiring matrix inversion. The N+1 processors may be reconfigured to multiply the auxiliary signals by the N weights during an active period of the primary signal when the component of interest is present in the primary signal. These weighted auxiliary signals are combined with the primary signal to provide a modified primary signal from which correlated interference in the auxiliary signals has been cancelled.
Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.
Abstract: A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a plurality of charge transfer channels in a parallel array. Charge transfer stages in those channels have corresponding charge storage sites facilitating charge transfer from each charge transfer stage to its corresponding charge storage site. Provisions are also made for charge transfer from each charge storage site back to its corresponding charge transfer stage or to a subsequent charge transfer stage. Such charge transfer schemes allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.
Abstract: A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the (N-1) input variables and their complements are arranged into 2.sup.(N-1) different combinations of (N-1) signals for generating a different combination of (N-1) signals per pair of logic gates. (N-1) inputs of each of the two gates forming a pair of gates are interconnected to receive the same N-1 input signals forming one of the 2.sup.N-1 combinations. The Nth input variable is applied to the Nth input of one gate from each pair of gates and the output of the one gate from each pair is connected to the Nth input of the other gate with which it is paired.
Abstract: An array of flared horn antennas is adapted to be fed from circular waveguide. The apertures of the horns are closely spaced. Prior art horns with circular apertures leave gaps in the aperture. The gaps are eliminated, and the gain of the array is increased by about 1/2 dB by tapering the horns from a circular cross-section at the feed end to a hexagonal cross-section at the radiating aperture end.
Abstract: A floating gate memory device includes a substrate of semiconductor material having on a surface thereof a layer of insulating material. On the insulating layer is a floating gate of conductive polycrystalline silicon with the floating gate having a textured outer surface and relatively smoother sidewalls. A second layer of insulating material extends over the outer surface and sidewalls of the floating gate. The portion of the second insulating material over the outer surface of the floating gate has a textured surface and is thinner than the portions of the second insulating layer over the sidewalls of the floating gate. A control gate is over the second insulating layer and extends over the outer surface and sidewalls of the floating gate. The control gate is of conductive polycrystalline silicon and has an inner surface portion over the textured outer surface of the control gate which is textured and has undulations which substantially follow the undulations of the textured surface of the floating gate.
Abstract: A pulse rate monitor comprises first and second units coupled by a cable. The first unit has a microwave ocillator that provides a pulsating DC signal in accordance with the pulse rate to the second unit which amplifies the signal. Since the first unit does not comprise microwave components other than the oscillator, it can be miniturized. The second unit also supplies power to the first unit.
Abstract: A multidisk spindle includes a plurality of mounting plates affixed to a shaft for mounting an equal plurality of record disks thereon such that the disks are parallel to each other and perpendicular to the rotational axis of the shaft. The shape of the mounting plates and their dimensions relative to the central apertures of the record disks permit the record disks to be mounted to the spindle after it has been fully assembled. In this way the assembled mounting plates may be abraded to provide plane disk-mounting surfaces which are parallel to each other and perpendicular to the axis of rotation.
Abstract: A phase shifter uses a PIN diode or diode pairs operated in a switching mode to switch transmission-line elements for phase-shifting radio frequency or microwave signals. A drive circuit for each diode(s) includes a FET switch controlled by a first level of a bilevel control signal to apply B+ to forward bias the diode(s) with a forward current. When forward biased, the active region of the diode(s) becomes flooded with charge carriers. The first FET switch is turned OFF by a second level of the bilevel control signal, and a second FET switch is turned ON to apply a reverse bias voltage to the diode(s) to render them nonconductive. Before the diode(s) become nonconductive, the excess charge carriers must be swept out of the diode(s). To achieve fast switching, the second FET switch must draw a large current for a short time as the excess charge carriers are removed.
October 11, 1985
Date of Patent:
June 28, 1988
Elmer L. Henderson, Henry F. Inacker, deceased, Michael P. Barnaba
Abstract: A first pattern of circular indicia of the same diameter and of equal spacing is superimposed with an overlapping second pattern of circular indicia of the same diameter as the first pattern indicia. The indicia of the second pattern are in progressively larger spacings in mirror image relation to a central reference indicia. Measurement indicia are adjacent to each indicia of the second pattern. Observation of the most closely aligned indicia of the first and second patterns and the measurement indicia corresponding to that most closely aligned indicia gives a quick visual measurement of the magnitude of the misalignment.
Abstract: An SOS integrated circuit includes a plurality of spaced islands of single-crystalline silicon on a surface of a sapphire substrate. A conformal layer of silicon oxide is on the surface of the sapphire substrate between the islands and extends along a portion of the side surfaces of the islands. A layer of polycrystalline silicon is over the silicon oxide layer and extends over the side surface and at least a portion of the top surface of the islands. A separate field-effect transistor is on each island and includes source and drain regions spaced by a channel region and a channel dielectric layer over the channel region. The polycrystalline silicon layer may extend over the channel dielectric to serve as the gate of the transistor. The method of making the circuit includes depositing the silicon oxide layer over the sapphire substrate surface and the islands, and applying a layer of a negative photoresist over the silicon oxide layer.
September 27, 1985
Date of Patent:
June 14, 1988
George L. Schnable, Kenneth M. Schlesier