Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes a push-pull output circuit including pull up and pull down transistors driven with separate control signals. A further transistor has its conduction path coupled between the control electrode and a point of potential of sufficient value to turn the pull up transistor off. The control electrode of the further transistor is coupled to an output of a succeeding one of the cascaded stages to insure that the output of the respective stage cannot drift to an on state.

Abstract: A compression/decompression system includes a source of (1:1 60 Hz) non-interlaced scanned video signal. A preprocessor constructs (2:1 60 Hz) interlaced scanned video signal from the non-interlaced scanned video signal by selection of alternate lines of successive non-interlaced image signals. The interlaced scanned video signal is compressed according to an MPEG protocol of I, P and B frame compression algorithms. I, P and B frame compression is performed such that there are an odd number, greater than one, of B-frames between successive I/P frames (for example the sequence of compressed frames may conform to I, B1, B2, B3, P, B1, B2, B3, P, B1, B2, B3, I, B1, . . . etc). The I compressed frames, the P compressed frames and alternate B compressed frames (the frames B2 in the exemplary sequence) selectively form a primary compressed (2:1 30 Hz) interlaced video signal for reproduction by interlaced scanned receivers. The intervening B-frames selectively form a secondary compressed video.

Abstract: Variable length codewords representing high definition television image information are processed by a codeword analyzr for prioritizing codewords within a predetermined codeword group. A single FIFO rate buffer conveys codewords subject to analysis to the analyzer. A succeeding codeword group is written into the buffer when a current codeword group is being analyzed, at which time buffer read out is inhibited. In an illustrated embodiment, buffer read out is inhibited, and codeword analysis begins, when MPEG Picture Start or Slice Start codewords associated with the succeeding codeword group approach the buffer output. Buffer read out is enabled at the end of the analysis interval.

Abstract: A full wave rectified AC mains supply voltage is produced from an AC mains supply voltage without low-pass filtering. The rectified voltage is developed in a winding of a flyback transformer. The winding of the flyback transformer is also coupled to a switching transistor that generates in the winding a first plurality of current pulses at a frequency that is higher than the frequency of the mains supply voltage. The current pulses energize a load circuit. A capacitor voltage is coupled via a second switching transistor to the winding to produce in the winding a second plurality of current pulses that energize the load circuit during a portion of the period of the mains supply voltage that does not occur in the vicinity of the peak of the mains supply voltage. When the second plurality of current pulses are generated, the mains supply voltage is decoupled from the first winding.

Abstract: Organ pipes distortions, caused by parasitic ringing in a horizontal deflection current are suppressed by forming a current pulse in a current injection arrangement. The current pulse is coupled to a junction terminal between a terminal of the horizontal deflection winding where a high retrace pulse voltage is developed and a low voltage terminal of a linearity correction inductance. A high voltage terminal of the linearity correction inductance is coupled to a horizontal output transistor. The current pulse begins prior to the end of retrace and ends during the trace interval. A modulation network is coupled across the linearity correction inductance for providing a low impedance current path to the current pulse.

Abstract: An East-West switching transistor is coupled between a flyback transformer primary winding and a horizontal deflection output transistor circuit to control retrace energy to obtain an East-West modulation of the deflection current amplitude as required for East-West pincushion raster correction. The East-West switching transistor isolates a retrace resonant circuit that includes a horizontal deflection winding from a flyback resonant circuit that includes the flyback transformer during a portion of retrace. The deflection winding is coupled to a common conductor to permit the use of a retrace voltage sample, developed in the deflection winding and coupled to the East-West switching transistor, to control the switching operation in a manner that bypasses the flyback transformer. A resistor coupled in series with the primary winding develops a voltage, during trace, that is indicative of beam current.

Abstract: A compression/decompression system includes a source of non-interlaced scanned video signal. A preprocessor constructs interlaced scanned video signal from the non-interlaced scanned video signal by selection of alternate lines of successive non-interlaced image signals. The interlaced scanned video signal is compressed according to known methods to generate primary compressed video data. The primary data is decompressed by known processes, inverse to the compression processes, to regenerate the interlaced scanned frames. Interlaced scanned video signal, corresponding to the intervening lines of the non-interlaced scanned video signal, which were not included in the primary interlaced scanned video signal, is predicted from the decompressed frames of video signal. In addition the intervening lines of the original non-interlaced scanned video signal, which were not included in the primary interlaced scanned video signal, are formed into secondary interlaced scanned video signal.

Abstract: Elements of the compressed video signal which are of greatest importance to signal decompression are set a plurality of times in redundant transport cells. Media error codes are concatenated to the redundant data such that when and if such redundant data is applied to the corresponding decompressor, the media error code will automatically force the decompressor to resynchronize.

Abstract: Error concealment apparatus for correcting errors in signals representing video images includes means for detecting image gradients in an area surrounding a lost block of image data. Circuitry responsive to these image gradients generates a plurality of blocks of directionally interpolated pixel values. The pixel values in the respective blocks of directionally interpolated pixel values are sorted according to amplitude, and then pixel values from mutually exclusive positions in the respective blocks are selected to form a block of pixel values for error concealment.

Abstract: A system for processing a high definition television signal includes a codeword prioritizer responsive to a codeword datastream derived from an MPEG-like encoder. The prioritizer generates a flag to indicate a breakpoint between high priority and standard priority codewords within a given image data group. Null codewords are inserted into the codeword datastream during intervals when the prioritizer is analyzing codewords to determine where to establish the priority breakpoint. The null codewords are ignored by a following transport processor which packs codewords into cells.

Abstract: A differential comparator includes first and second transistors for comparing an input signal to a reference signal during a comparison phase and circuitry for balancing the quiescent currents through the transistors. The circuitry includes a first current source connected to the source of the first transistor, a second current source connected to the source of the second transistor and a selectively enabled impedance means connected between the sources of the two transistors. Prior to each comparison phase the currents through the first and second transistors are balanced (i.e. made approximately equal) by application of equal voltages to the gates of the two transistors and cross-coupling the source potentials of the first and second transistors to control the second and first current sources.

Abstract: A pulse-width modulator controls a switching transistor. The switching transistor is coupled to a primary winding of a chopper transformer. The switching transistor and the primary winding are referenced to a nonisolated ground conductor. To initiate a standby mode of operation, a first on/off control signal that is referenced to an isolated ground conductor disables a horizontal oscillator that is energized from a secondary winding of the chopper transformer and that is also referenced to the isolated ground conductor. As a result, a decrease loading of circuit elements that are referenced to the isolated ground occurs. In the standby mode, current pulses in the primary winding are produced at a substantially higher frequency than in normal operation. A frequency detector referenced to the nonisolated ground generates a second on/off control signal that is referenced to the nonisolated ground in accordance with the frequency of the current pulses in the chopper transformer.

Abstract: In a switch mode power supply, a full wave rectified AC mains supply voltage is produced from an AC mains supply voltage without low-pass filtering. The unfiltered rectified voltage is applied to a winding of a flyback transformer that is coupled to a switching transistor. A first plurality of current pulses are generated in the winding from the rectified voltage at a frequency that is higher than the frequency of the mains supply voltage and at peak amplitudes that vary in accordance with the rectified voltage in a manner to increase a power factor. The rectified voltage is further rectified via a rectifier coupled in series with a resistor and a low-pass filter capacitor and produces current pulses in the capacitor. A voltage in the capacitor is coupled via a second switching transistor to the winding to produce in the winding a second plurality of current pulses that reduce a ripple component at an output of the power supply.

Abstract: A video input signal is applied to a bridged-T attenuator which includes a non-linear element in the shunt branch thereof that provides increasing attenuation as the input signal increases to thereby produce a gamma corrected video output signal at the attenuator output. A current sensor in the shunt branch generates an exponentially increasing detail signal for increases in the video input signal. The detail signal is high pass filtered and combined with the gamma corrected signal by a summing circuit for providing a video output signal having gamma correction and high frequency detail augmentation.

Abstract: In a switch mode power supply, a full wave rectified AC mains supply voltage is produced from an AC mains supply voltage without low-pass filtering. The unfiltered rectified voltage is applied to a winding of a flyback transformer that is coupled to a switching transistor. A first plurality of current pulses are generated in the winding from the rectified voltage at a frequency that is higher than the frequency of the mains supply voltage and at peak amplitudes that vary in a manner to reduce a power factor. A second supply voltage is applied via a second switching transistor to the winding to produce in the winding a second plurality of current pulses that reduce a ripple component at an output of the power supply. The second plurality of current pulses are pulse-width modulated in a feed-forward manner during a period of the mains supply voltage in accordance with the mains supply voltage.

Abstract: A known system derives information from the VPS- and Teletext signals and displays the title of the current program and the network name on screen for a few seconds, each time a new channel is selected. The VPS- and Teletext signals contain more program-related information than mentioned above. The present invention concerns deriving the end-time and/or the remaining duration of the current program as well as the starting-time of the next program for display on-screen.

Abstract: A ghost cancelling system includes a ghost cancelling IIR filter and channel modelling circuitry for generating tap weighting coefficients for programming the ghost cancelling IIR filter. The channel modelling circuitry includes means for calculating the sum of all of the generated weighting coefficient values. If the sum exceeds a predetermined value indicative of the IIR filter becoming unstable, the weighting coefficients are conditionally scaled in a manner to reduce the sum, thus tending to reduce the possibility of filter instability.

Abstract: A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node.

Abstract: A compression/decompression system includes a source of (1:1 60 Hz) non-interlaced scanned video signal. A preprocessor constructs (2:1 60 Hz) interlaced scanned video signal from the non-interlaced scanned video signal by selection of alternate lines of successive non-interlaced image signals. The interlaced scanned video signal is compressed according to an MPEG protocol of I, P and B frame compression algorithms. I, P and B frame compression is performed such that there are an odd number, greater than one, of B-frames between successive I/P frames (for example the sequence of compressed frames may conform to I, B1, B2, B3, P, B1, B2, B3, P, B1, B2, B3, I, B1, . . . etc). The I compressed frames, the P compressed frames and alternate B compressed frames (the frames B2 in the exemplary sequence) selectively form a primary compressed (2:1 30 Hz) interlaced video signal for reproduction by interlaced scanned receivers. The intervening B-frames selectively form a secondary compressed video.

Abstract: A deflection apparatus includes a pair of quadrupole arrangements for producing a pair of quadrupole fields in a beam path of an electron beam at different distances from a display screen. In an embodiment of the invention, the first and second quadrupole arrangements and a main deflection field producing arrangement cooperate to converge three electron beams, R, G and B, with one another.