Abstract: A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.

Abstract: An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.

Abstract: A control device for a servo motor system is provided. The control device includes a segment parameter storage circuit, a velocity superposing circuit, a velocity transferring circuit and a pulse comparison circuit. The segment parameter storage circuit is electrically connected with the velocity superposing circuit and the pulse comparison circuit. The velocity transferring circuit is connected between the velocity superposing circuit and the pulse comparison circuit. The velocity superposing circuit updates a present velocity value according to a target velocity value and an increment. The velocity transferring circuit generates a PWM signal according to the present velocity value. The pulse comparison circuit transfers the PWM signal into a signal of a command pulse wave group and judges whether a pulse number of the PWM signal reaches a predetermined pulse number.

Abstract: A signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a first output signal according to a gain; a first magnitude detector receiving the first output signal and generating a first magnitude signal; a first adder for subtracting the first magnitude signal from a reference value, thereby generating a first sampling signal; and a first weighting integrator receiving the first input signal, the second input signal and the first sampling signal, and generating the first integrated signal to control the gain of the first gain-adjustable amplifier.

Abstract: A signal processing apparatus receiving a first input signal and the first input signal being directly used as a first output signal. The signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a gain-adjusted first input signal according to a gain; a first adder for subtracting the gain-adjusted first input signal from the second input signal, thereby generating a second output signal; and a weighting correlator receiving the first output signal and the second output signal, and generating the first integrated signal to control the gain.

Abstract: A signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a gain-adjusted first input signal according to a first gain; a first adder for subtracting the gain-adjusted first input signal from the second input signal, thereby generating a second output signal; a second gain-adjustable amplifier receiving the second input signal and generating a gain-adjusted second input signal according to a second gain; a second adder for subtracting the gain-adjusted second input signal from the first input signal, thereby generating a first output signal; and a weighting correlator receiving the first output signal and the second output signal, and generating the first integrated signal to control the first gain and the second gain.

Abstract: A signal processing apparatus includes an adder and a weighting integrator. The adder receives a first input signal and an integrated signal, and generates a first output signal. The first output signal is obtained by subtracting the integrated signal from the first input signal. The weighting integrator receives the first output signal, and generates the integrated signal. The weighting integrator includes a weighting function generator, a multiplier, and an accumulator. The weighting function generator receives the first output signal. When the first output signal crosses a zero crossing point, the weighting function generator generates a weighting function. The multiplier performs a multiplication on the weighting function and the first output signal. The accumulator is connected to the multiplier for accumulating the product of the weighting function and the first output signal, thereby generating the integrated signal.

Abstract: A DC offset cancellation circuit is provided. A first DC current and a first sensing current are superposed with each other to generate a first superposed current. A second DC current and a second sensing current are superposed with each other to generate a second superposed current. The first superposed current is converted into a first voltage signal. The second superposed current is converted into a second voltage signal. After the first voltage signal and the second voltage signal are received by a differential amplifier, an output signal is generated. The output signal is processed into a DC value. The DC value is converted into a DC current signal. The superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.

Abstract: A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.

Abstract: A battery status indicating method for an electronic device is provided. The battery module is pluggable into the electronic device. When a residual electric quantity of the battery module is lower than a threshold electric quantity, the battery module stops outputting a battery voltage. The battery status indicating method includes steps of judging whether the battery module is in a plugged status or an unplugged status according to the battery voltage, periodically charging the battery module in a first time interval of a fixed cycle if the battery module is in the unplugged status, and judging whether the battery module is switched to the unplugged status according to a change of the battery voltage if the battery module is in the plugged status.

Abstract: A pulse processor includes a phase/pulse width sampler, a first calculator, a second calculator, a latching device, and a pulse width modulator. The phase/pulse width sampler generates an input direction signal, an input phase number and an input pulse width number according to a first signal and a second signal of the command pulse group. The first calculator is used for multiplying the input phase number by P/Q, thereby generating a target phase number, wherein P and Q are positive integers. The second calculator is used for multiplying the input pulse width number by Q/P, thereby generating a target pulse width number. The latching device receives the input direction signal and outputs a target direction signal. The pulse width modulator receives the target direction signal, the target phase number and the target pulse width number, and outputs a transferred pulse group.

Abstract: A pulse processor includes a phase/pulse width sampler, a first calculator, a second calculator, a latching device, and a pulse width modulator. The phase/pulse width sampler generates an input direction signal, an input phase number and an input pulse width number according to a first signal and a second signal of the command pulse group. The first calculator is used for multiplying the input phase number by P/Q, thereby generating a target phase number, wherein P and Q are positive integers. The second calculator is used for multiplying the input pulse width number by Q/P, thereby generating a target pulse width number. The latching device receives the input direction signal and outputs a target direction signal. The pulse width modulator receives the target direction signal, the target phase number and the target pulse width number, and outputs a transferred pulse group.

Abstract: A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.

Abstract: A register renaming table recovery method for use in a processor includes the following steps. Firstly, a flushing operation is performed on a renaming-history table according to a flushed ID. Then, a first renamed ID corresponding to a first register is acquired from an unflushed row of the renaming-history table that is immediately adjacent to the flushed ID. If the first renamed ID is occupied, a register renaming table is updated to rename the first register according to the first renamed ID. Whereas, if the first renamed ID is not occupied, the register renaming table is updated to keep the first register unrenamed.

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract: A battery status indicating method for an electronic device is provided. The battery module is pluggable into the electronic device. When a residual electric quantity of the battery module is lower than a threshold electric quantity, the battery module stops outputting a battery voltage. The battery status indicating method includes steps of judging whether the battery module is in a plugged status or an unplugged status according to the battery voltage, periodically charging the battery module in a first time interval of a fixed cycle if the battery module is in the unplugged status, and judging whether the battery module is switched to the unplugged status according to a change of the battery voltage if the battery module is in the plugged status.

Abstract: A data writing method and a micro-operation processing system are provided. The micro-operation processing system is adapted to access a plurality of registers and each of the registers defines at least one logic storing area. The data writing method comprises the following steps: executing a first micro-operation; selecting a target area of the first micro-operation, which has been updated by the second micro-operation before, as one of the logic storing areas; assigning each of the first micro-operation and the second micro-operation a respective identification number; determining that a execution order of the first micro-operation is later than a execution order of the second micro-operation according to the identification numbers of the first micro-operation and the second micro-operation; and recording that the target area has been updated by the first micro-operation.

Abstract: An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit.

Abstract: In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is set as a gravity point to attract an input of the (N+1)th 2-pin logic cell, thereby optionally flipping the (N+1)th 2-pin logic cell.

Abstract: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.