Abstract: In a data rearranging method for performing a distribution processing of an array in a multi processor system including a plurality of processors each of which has an independent memory, there are included the following steps of collecting data distribution formats that indicate schemes of allocating the respective array elements to the distributed-memories at the respective points in a program, and subdividing the array into a set of subarrays, each of the subarrays belonging to only one processor in any one of the data distribution formats obtained at the above-described format collecting step, and increasing the number of dimensions of the original array and rearranging sequence of array elements so that the array elements within each of the above-described subarrays possess consecutive addresses.

Abstract: A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal, a core logic carry generation output terminal, a core logic carry propagation output terminal, a ripple-core logic carry input terminal, and a sum output terminal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit.

Abstract: A programmable function block 20 comprises a logic block 21 including a full adder 31 and at least one preposition logic 32, and an input block 22 including programmable input switch units 40-1 through 40-9 for use in selectively switching a HIGH logic level signal, a LOW logic level signal, and a signal on interconnection lines 50. The preposition logic 32 comprises an exclusive OR circuit 32-1 and a multiplexer 32-2 and functions as various different logic circuits by means of setting some of the inputs thereof to a HIGH logic level or a LOW logic level. Thus, the logic block functions as various different logic circuits depending on the state of the inputs. In addition, the full adder provides fast arithmetic operation.

Abstract: A system comprising a neural network, or computer, implementing a feature detection and a statistical procedure, together with fuzzy logic for solving the problem of recognition of faces or other objects) at multiple resolutions is described. A plurality of previously described systems for recognizing faces (or other objects) which use local autocorrelation coefficients and linear discriminant analysis are trained on a data set to recognize facial images each at a particular resolution. In a second training stage, each of the previously described systems is tested on a second training set in which the images presented to the previously described recognition systems have a matching resolution to those of the first training set, the statistical performance of this second training stage being used to train a fuzzy combination technique, that of fuzzy integrals.

Abstract: The present invention is intended to provide an image recognition method which, in recognizing an input image including an object presumable to have continuity like a human figure, enables simultaneously detecting the shape of the object in the input image and cutting-out the object therefrom, and obtaining information on position of the object at the same time, and which also enables recognition of two objects having the same shape but having different sizes.

Abstract: A speech recognition system automatically designates a scope of a partial reference pattern. Plural reference patterns, each of which ends in each of composing frames and starts from a preceding frame, are supposed and cumulative distances at every frame are calculated. A partial reference pattern that has a minimal distance value as compared with all other partial reference patterns is taken as a partial input speech recognizing result.

Abstract: A speech and moving image search apparatus includes an input section for inputting a command and a label information storage device for storing label information. A label attribute storage device is further included for storing label attributes, as well as a broader term storage device for storing broader terms of labels. A first search section extracts information on the data from the label information storage device. A database is also included for storing speech and moving images. A control section thereafter accesses desired data in the database based on the information extracted by the first search section. Finally, an output section is included for outputting the data.