Abstract: A stacked inductor device including an 8-shaped inductor structure a stacked coil. The 8-shaped inductor structure includes a first coil and a second coil. The first coil is disposed in a first area. The first coil includes a first sub-coil and a second sub-coil, and the first sub-coil and the second sub-coil are disposed with an interval circularly with each other. The second coil is disposed in a second area, and the second coil is coupled with the first coil on a boundary between the first area and the second area. The second coil includes a third sub-coil and a fourth sub-coil, and the third sub-coil and the fourth sub-coil are disposed with an interval circularly with each other. The stacked coil is coupled to the first coil and the second coil and is stacked partially on or under the first coil and the second coil.

Abstract: A transmitting circuit, which includes a power amplifier, a processing circuit, and a signal strength indicator circuit. The power amplifier is configured to amplify an input signal according to a power gain of the power amplifier to generate an output signal. The processing circuit is configured to adjust the power gain according to an indicating signal. The signal strength indicator circuit has a plurality of power detection ranges. The signal strength indicator circuit is configured to uses one of the plurality of power detection ranges to detect a power of the output signal to generate the indicating signal.

Abstract: A display updating system and a display are provided. The display updating system includes a display and an electronic device. The display includes a display panel, a USB hub, and a display control circuit. The USB hub is configured to receive a plurality of display program codes through a USB interface. The display control circuit is configured to receive the display program codes from the USB hub and store the display program codes. The electronic device is connected to the display through the USB interface and includes a memory, a USB driver circuit, and a calculation circuit. The memory is configured to store the display program codes. The USB driver circuit is connected to the USB hub of the display through the USB interface. The calculation circuit is configured to control the USB driver circuit to transmit the display program codes through the USB interface.

Abstract: A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.

Abstract: The present invention discloses an electronic apparatus operation method having elastic boot file allocation mechanism that includes steps outlined below. A system activation procedure is executed by a processing circuit to load a hard code setting data from a boot code block of a boot data storage circuit to a system storage circuit. Version setting data is loaded to the system storage circuit to replace at least a part of the hard code setting data to generate boot setting data by the processing circuit when the version setting block is determined to include the version setting data by the processing circuit. The system activation procedure is proceeded to be executed according to the boot setting data by the processing circuit.

Abstract: A timing recovery method includes the following operations: performing a time domain timing recovery process according to a predefined cyclic prefix portion of a first symbol during a downstream time-division duplexing frame period to tune a phase locked loop circuit; and performing a frequency domain timing recovery process according to at least one second symbol that follows the first symbol during the downstream time-division duplexing frame period to tune the phase locked loop circuit.

Abstract: An analog to digital convertor circuit includes an input circuit and a switched capacitor circuit. The input circuit is configured to selectively drain a first current from a first node or drain a second current from a second node according to a first bit and a second bit that have opposite logic values. The switched capacitor circuit is configured to compensate a capacitance value of one of the first node and the second node according to the first bit and the second bit.

Abstract: An inductive unit is formed in an integrated circuit. An electromagnetic radiation test is performed thereon. When an amount of electromagnetic radiation exceeds a radiation threshold value, a shielding structure is formed. The shielding structure has a width and a distance separated from the inductive unit such that a decreasing amount of a quality factor of the inductive unit is not larger than a first predetermined value and a shielded amount of electromagnetic radiation is not lower than a second predetermined value. The inductive unit has a symmetric shape and the inductive device further includes a single asymmetric inductive portion. The closed shape of the shielding structure encloses the inductive unit and covers the single asymmetric inductive portion. A part of the single asymmetric inductive portion extends along a peripheral direction of the shielding structure.

Abstract: A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.

Abstract: A low dropout regulator includes an output circuit and an amplifier. The output circuit includes a signal input end configured to receive an input voltage and a signal output end configured to output an output voltage. The amplifier includes a first stage amplifier circuit, a second stage amplifier circuit, a first feedback circuit and a second feedback circuit. The first stage amplifier circuit includes a positive output end and a negative output end. The second stage amplifier circuit includes an input end and an output end, wherein the input end and the positive output end are coupled at a first node, and the output end is coupled to the output circuit. The first feedback circuit is coupled between the negative output end and the output end. The second feedback circuit is coupled between the first node and the output end.

Abstract: The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.

Abstract: A processor chip includes a logic circuit. The logic circuit is configured to be coupled to an electronic device. A configuration of the logic circuit corresponds to a plurality of candidate configurations. The configuration of the logic circuit is switched among the candidate configurations, and the electronic device associates with the processor chip to implement a function corresponding to the configuration of the logic circuit. When the configuration of the logic circuit is a first configuration and the electronic device executes a first driver program, the function is a first network-connection function. When the configuration of the logic circuit is a second configuration and the electronic device executes a second driver program, the function is a second network-connection function different from the first network-connection function.

Abstract: An inductor device includes a first trace, a second trace, a third trace, a fourth trace, and a double ring inductor. The first trace is disposed in a first area, and located on a first layer. The second trace is disposed in the first area, coupled to the first trace, and located on a second layer. The third trace is disposed in a second area, and located on the first layer. The fourth trace is disposed in the second area, coupled to the third trace, and located on the second layer. The double ring inductor is disposed on the first layer, located at outer side of the first trace and the third trace, and coupled to the first trace and the third trace.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates a reference clock signal. A fake data strobe signal generation circuit receives the reference clock signal and delays a read enable signal from a memory access controller to enable an output of the reference clock signal to generate a fake data strobe signal. A real data strobe signal generation circuit receives a data strobe signal from a memory device and delays the read enable signal to enable an output of the data strobe signal to generate a real data strobe signal. A data reading circuit samples a data signal from the memory device according to a sampling signal to generate a read data signal to the memory access controller. A selection circuit selects the fake and the real data strobe signals as the sampling signal respectively under a single and a double data rate modes.

Abstract: Audio amplifier circuit includes a pulse width modulation circuit, an auxiliary loop circuit corresponding to a first variable resistance value and a first variable current value, and a main loop circuit corresponding to a second variable resistance value and a second variable current value. Main loop circuit is coupled between a second node, an output terminal, and a first node. Under a condition that auxiliary loop circuit and main loop circuit are turned on, second variable resistance value is decreased and second variable current value is increased after auxiliary loop circuit enters into a first control state, such that main loop circuit enters into a second control state. First variable resistance value is increased and first variable current value is decreased after main loop circuit enters into second control state, such that auxiliary loop circuit is out of first control state.

Abstract: A storage device includes a controller and a memory. A method of storage space management for the storage device is executed to perform steps as below. The controller calculates an expectedly used capacity and an effective capacity of the memory. The controller determines whether blocks of the memory include one or more blocks that are non-bad blocks and are prohibited from reading/writing. When the one or more blocks are determined to be non-bad blocks and to be prohibited from reading/writing, the controller marks each of the one or more blocks as a restricted block other than a bad block, thereby maintaining the effective capacity to be unchanged. The controller compares difference of the effective capacity and a total capacity of the one or more blocks that are marked as the restricted block to the expectedly used capacity to determine whether to prohibit programming to the memory.

Abstract: A content addressable memory cell includes storage circuits and a comparator circuit. A first storage circuit of the storage circuits is configured to store data, and a second storage circuit of the storage circuits is configured to store a state bit. The comparator circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the state bit in response to levels of search bit lines and another one of the data and the state bit.

Abstract: The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ?P?.

Abstract: An embedded system includes a host controller circuit and a microcontroller circuit. The host controller circuit is configured to access a storage device to obtain an address of a first firmware file in the storage device. The microcontroller circuit is configured to determine whether a memory circuit is being accessed by other circuits, in which the memory circuit includes memory blocks. If the memory circuit is not being accessed by the other circuits, the microcontroller circuit is further to control the host controller circuit to write the first firmware file to a first block of the memory blocks according to the address.

Abstract: A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal.