Patents Assigned to RealTek Semiconductor Corporation
  • Patent number: 11910312
    Abstract: The present application provides a method for a WiFi module and system of the same. The method including: determining whether a specific process is a high-power consumption event; and when the specific process is determined as the high-power consumption event, performing a time-divisional operation upon the specific process. The present application further provides another method for a WiFi module, including: determining whether a specific process is a high-power consumption event; and when the specific process is determined as the high-power consumption event, estimating a first power consumption request information and transmitting the information to a control module of a local end; and receiving a first response corresponding to the first power consumption request information from the control module.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: February 20, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Zhaoming Li, Mengzhou Shen, Zuohui Peng, Guofeng Zhang
  • Patent number: 11907738
    Abstract: An image processing method applied to a display device having a processing circuit and a screen and includes: receiving a first image from one of a plurality of electronic devices; detecting whether the first image has a black border area; and if the first image has the black border area, performing a first display operation, wherein performing the first display operation includes: removing the black border area of the first image, to generate a second image; adjusting the size of the second image according to the size of a display area of the screen; calculating a first blank area of the screen based on the adjusted second image; requesting a third image from another one of the electronic devices according to the size of the first blank area; and filling the display area of the screen with the adjusted second image and the third image.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: February 20, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Yuh-Wey Lin, Chun-Hao Huang
  • Patent number: 11901804
    Abstract: A power supplying circuit includes a first high-voltage switch, a first low-voltage switch, a second high-voltage switch, a second low-voltage switch, and a controller circuit. The first high-voltage switch receives a first input voltage and generates a first node voltage. The first low-voltage switch is coupled between the first high-voltage switch and an output terminal. The second high-voltage switch receives a second input voltage and generates a second node voltage. The second low-voltage switch is coupled between the second high-voltage switch and the output terminal. The controller circuit controls the first high-voltage switch, the first low-voltage switch, the second high-voltage switch, and the second low-voltage switch according to the first node voltage and the second node voltage such that an output voltage is outputted to the output terminal.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: February 13, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Jiun Hung Pan, Leaf Chen
  • Patent number: 11901111
    Abstract: An inductor device includes a first wire, a second wire, at least one first connector, at least one second connector, and a first center-tapped terminal. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The first sub-wires and the second sub-wires are disposed in an interlaced manner. The at least one first connector couples the first sub-wire that is disposed on an outer side and the first sub-wire that is disposed on an inner side in the first sub-wires. The at least one second connector couples the second sub-wire that is disposed on the outer side and the second sub-wire that is disposed on the inner side in the second sub-wires. The first center-tapped terminal is coupled to the first sub-wire that is disposed on the outer side in the first sub-wires.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Kuan-Yu Shih, Ka-Un Chan
  • Patent number: 11900953
    Abstract: An audio processing method includes the following operations. A calculated value is obtained according to multiple audio clock frequency information contained in multiple audio input packets. An audio sampling frequency is generated according to the calculated value and a link symbol clock signal. Multiple audio output packets corresponding to the audio input packets are generated according to the audio sampling frequency.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chang Liu, Jing-Chu Chan, Hung-Yi Chang
  • Patent number: 11901399
    Abstract: A semiconductor device includes a first coil, a second coil, and a third coil. The second coil is disposed with respect to the first coil. The third coil is configured to sense a signal on the first coil. A first overlapped area, on a projection plane, of the third coil and the first coil is larger than a second overlapped area, on the projection plane, of the third coil and the second coil.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 11899049
    Abstract: The present invention discloses a comparison circuit having adaptive comparison mechanism is provided. A comparator is enabled by an enabling signal having an enabling state during a comparison stage to compare a first voltage and a second voltage to generate a comparison result. A comparison determining circuit sets a stage indication signal at an unfinished state and a finished state before and after the comparison result is generated. A time accumulating circuit starts to accumulate an accumulated time when the enabling signal is at the enabling state and stops accumulating when the stage indication signal is at the finished state to generate a comparison time. A determining circuit performs statistics on the comparison time to generate a predetermined threshold time and sets a predetermined comparison result as the comparison result under the condition that the comparison result is not generated and the accumulated time exceeds the predetermined threshold time.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 11901866
    Abstract: An amplifier circuit, which has a first output terminal and a second output terminal, includes a first charge-steering amplifier, a second charge-steering amplifier, a first switch, and a second switch. The first charge-steering amplifier includes a first input terminal, a second input terminal, a first capacitor, and a second capacitor, and is used for amplifying a first input signal in a first operation period. The second charge-steering amplifier includes a third input terminal, a fourth input terminal, the first capacitor, and the second capacitor, and is used for amplifying a second input signal in a second operation period. The first capacitor and the second capacitor charge during the first operation period and discharge during the second operation period.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 11901870
    Abstract: An amplifier includes an amplifier circuit and a gain adjusting circuit. The amplifier circuit has a design gain and a real gain and is configured to output an output signal according to an input signal and the real gain. The gain adjusting circuit is coupled to the amplifier circuit and is configured to receive the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the real gain of the amplifier circuit, so that the real gain approach the design gain.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ming-Hui Tung, Shawn Min
  • Patent number: 11895434
    Abstract: A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 6, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Hsin Lin, Wen-Hsia Kung
  • Patent number: 11895358
    Abstract: The present invention discloses a signal output circuit having DC gain maintaining mechanism used in an image signal transmission apparatus that includes a front-stage driving circuit and a back-stage driving circuit. The front-stage driving circuit includes a continuous time linear equalizer (CTLE) having an adjusting capacitor and configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a front-stage output signal. The back-stage driving circuit includes a CTLE without the adjusting capacitor and configured to increase a DC gain of the front-stage output signal to compensate a DC gain drop between the front-stage output signal and the digital input signal to generate a back-stage output signal to an image signal receiving apparatus.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 6, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Ming-Hui Tung
  • Patent number: 11894856
    Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 6, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsuan-Ting Ho, Liang-Wei Huang, Yun-Chih Tsai, Chia-Lin Chang
  • Patent number: 11888755
    Abstract: A multidrop network system includes N network devices. The N network devices includes M transmission-permissible devices including a master device and at least one slave device, wherein M is not greater than N. Each transmission-permissible device has at least one identification code as its identification in the multidrop network system, and the M transmission-permissible devices have at least N identification codes. The M transmission-permissible devices obtain transmission opportunities in turn according to their respective identification codes in each round of data transmission. A Kth device among the M transmission-permissible devices has multiple identification codes, and thus obtains multiple transmission opportunities in one round of data transmission.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 30, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Le Chang, Wen-Chih Fang, Deng-Shian Wang, Shieh-Hsing Kuo
  • Patent number: 11882030
    Abstract: The present disclosure provides a network packet transmission device and a network packet transmission method thereof. The network packet transmission method includes: receiving a network packet, wherein the network packet has at least one packet attribute; determining at least one destination VID for the network packet according to the at least one packet attribute; determining a transmission speed corresponding to the at least one destination VID based on at least one LAN speed table; and transmitting the network packet to a VLAN corresponding to the at least one destination VID according to the transmission speed.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: January 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Mei Yue Wang, Juan Liu, Hang Chi
  • Patent number: 11876526
    Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Kai-Yue Lin, Wei-Jyun Wang, Sheng-Yen Shih
  • Patent number: 11875779
    Abstract: Disclosed is a voice activity detection (VAD) device and method capable of referring to an environment detection result and thereby selecting one of multiple VAD results as a basis for determining whether a voice activity occurs. The VAD device includes an environment detection circuit, a VAD circuit, and a voice activity decision circuit. The environment detection circuit is configured to process an audio input signal and thereby generate an environment detection result. The VAD circuit is configured to analyze the audio input signal with multiple VAD algorithms and thereby generate multiple VAD results. The voice activity decision circuit is configured to select one of the multiple VAD results according to the environment detection result.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: January 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yi-Cheng Huang
  • Patent number: 11876113
    Abstract: An integrated transformer is provided. The integrated transformer includes a first inductor and second inductors. The first inductor includes a first winding having a first outer turn and a second winding having a second outer turn. The second inductor includes a third winding having a third outer turn and a fourth winding having a fourth outer turn. The first and third outer turns substantially overlap, and the second and fourth outer turns substantially overlap. The first and second outer turns are connected to each other through a first segment and a second segment that together form a crossing structure, and the third and fourth outer turns are connected to each other through a third segment and a fourth segment that together form a crossing structure. The first and third segments are in the first metal layer, while the second and fourth segments are in the second metal layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ka-Un Chan
  • Patent number: 11869700
    Abstract: An inductor device includes first trace, second trace, third trace, fourth trace, first capacitor, and second capacitor. One terminal of each of the at least two sub-traces of first trace are coupled to each other at first node. One terminal of each of the at least two sub-traces of second trace are coupled to each other at second node. One terminal of third trace is coupled to second trace, and another terminal of third trace is coupled to first input/output terminal. One terminal of fourth trace is coupled to first trace, and another terminal of fourth trace is coupled to second input/output terminal. First capacitor is coupled to first node and second node. Second capacitor is coupled between first node and first input/output terminal, or coupled between first node and second input/output terminal, or coupled between first input/output terminal and second input/output terminal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 9, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Jian-You Chen, Ka-Un Chan
  • Patent number: 11868150
    Abstract: The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 9, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hsi-En Liu
  • Patent number: 11869168
    Abstract: A method for optimizing a display image based on display content is provided. The method is applicable to a display control chip, and includes following operations: receiving a video signal configured to transmit an image of a frame; with respect to multiple different sub-areas in an area of the image, calculating a pixel number distribution of each sub-area along multiple characteristic values; determining, according to the pixel number distribution, whether the sub-area comprises a corresponding first target pattern of multiple first target patterns; if the multiple sub-areas comprise the multiple first target patterns, respectively, performing a first preset image processing to the image to generate a processed image; if the multiple sub-areas are free from comprising the multiple first target patterns, respectively, omitting the first preset image processing to the image; and generating a display signal according to the processed image or the image.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 9, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Yuh-Wey Lin, Jui-Te Wei