Abstract: A capacitive sensing device includes a switch circuitry, a counter circuit, a comparator circuit, an amplifier circuit including first and second input terminals and an output terminal, and a feedback capacitor coupled between the output terminal and the first input terminal. The switch circuitry transmits a reference voltage to the second input terminal and couples the first input terminal to the output terminal during a first phase, transmits another reference voltage to the second input terminal during a second phase, and adjusts a voltage of the output terminal during a third phase. The counter circuit starts counting and the comparator circuit generates the control signal according to the output voltage and the second reference voltage during the third phase. The counter circuit stops counting according to the control signal to generate a count value indicating a capacitance value change of a capacitor under-test coupled to the first input terminal.

Abstract: A temperature sensing circuit that includes a bandgap voltage generation circuit, a current mirror branch, a variable resistor, a comparator circuit, a control circuit and a temperature determining circuit. The bandgap voltage generation circuit generates a bandgap voltage. The current mirror branch generates a mirrored current mirrored from the bandgap voltage generation circuit. The variable resistor is electrically coupled to the current mirror branch to receive the mirrored current to generate a variable voltage. The comparator circuit compares the bandgap voltage and the variable voltage to generate a comparison result. The control circuit generates a control signal according to the comparison result to adjust the resistance of the variable resistor and outputs a signal value when the signal value forces the variable voltage to be equal to the bandgap voltage. The temperature determining circuit generates a temperature value according to the signal value.

Abstract: A method for developing an Android TV hybrid application includes: generating a WebView component in an Android Activity belonging to an Android side of the application; obtaining a WebSettings subclass and using it to configure the WebView component; using Web technologies to develop a Web page belonging to a Web side of the application; using the WebView component to show the Web page; creating a first Java object blended with a JavaScript context in the Android side to define different interfaces, and creating a second Java object to implement the interfaces defined by the first Java object, so that the Web side can call the functions of the Android side; providing a packaged Java class in the Android side to send messages, and providing a packaged JavaScript module in the Web side to process the messages, so that the Android side can feedback the messages to the Web side.

Abstract: The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.

Abstract: A chip includes a first circuitry and a second circuitry. The first circuitry includes first circuits which have first power consumption at a point of time. The second circuitry includes second circuits which have second power consumption at the point of time, and the first power consumption is higher than the second power consumption. At least one of the first circuits and at least one the second circuits are alternately arranged, in order to lower an operating temperature of the plurality of first circuits at the point of time.

Abstract: A monitor control method is used for controlling a monitor and includes the following steps: controlling the monitor to display a pattern; selecting, in response to a selection signal, one of a plurality of brightness curves as a target brightness curve, or generating by interpolation the target brightness curve; and controlling the brightness of the monitor according to the target brightness curve.

Abstract: A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.

Abstract: A power amplifier includes a power switching circuit, a driver circuit, and an amplifier circuit. The power switching circuit is configured to receive a first voltage and a second voltage, and provide the first voltage or the second voltage according to an operation mode of the power amplifier. The driver circuit is coupled to the power switching circuit. The driver circuit is configured to operate according to the first voltage or the second voltage and generate a driving signal according to an input signal. The amplifier circuit is coupled to the power switching circuit and the driver circuit. The amplifier circuit is configured to operate according to the first voltage or the second voltage and generate an output signal according to the driving signal.

Abstract: An inductor device includes a first and a second inductor and a first and a second connection member. A first and a second trace of the first inductor is located on a first and a second layer respectively. The second trace is coupled to the first trace located at a first and a second area. The first connection member is coupled to the second trace. A third and a fourth trace of the second inductor is located on the first and the second layer respectively. The first trace and the third trace are disposed in turn at the first area and the second area. The fourth trace is coupled to the third trace located at the first and the second area. The second and the fourth trace are disposed in turn at the first and the second area. The second connection member is coupled to the fourth trace.

Abstract: An operation method of a network device and a control chip of the network device are provided. The network device receives an input signal through a fiber medium. The operation method includes the following steps: setting a target speed of the network device to a first speed; transmitting and/or receiving a data at the first speed; and setting the target speed of the network device to a second speed which is different from the first speed when the amplitude or energy of the input signal is not greater than a threshold.

Abstract: A multidrop network system includes N network devices. The N network devices include a master device and multiple slave devices, and each network device has an identification code as its own identification in the multidrop network system. The N network devices have N identification codes and obtain transmission opportunities in turn according to the N identification codes in each round of data transmission. Each network device performs a count operation to generate a current count value, and when the identification code of a network device is the same as the current count value, this network device obtains a transmission opportunity. After a device obtains the transmission opportunity, it determines whether a cut-in signal from another network device is observed in a front duration of a predetermined time slot, and then determines whether to abandon/defer the right to start transmitting in the remaining duration of the predetermined time slot.

Abstract: A chip having a debug function includes functional circuitries, a selector circuitry, a data reconstruction circuitry, and a switching circuitry. Each functional circuitry includes a decoder circuit that stores a corresponding set of debug signals and outputs a corresponding debug signal in the corresponding set of debug signals to be a corresponding signal in first signals according to a corresponding address signal in address signals. The selector circuitry selects second signals from the first signals according to the address signals. The data reconstruction circuitry selects first data from the second signals according to split signals and outputs the same to be debug data. Each first data is partial data of a corresponding signal in the second signals. The switching circuitry determines whether to output the debug data or at least one output signal associated with the functional circuitries via output ports according to switching signals.

Abstract: A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.

Abstract: An antenna structure includes a first resonant unit and a second resonant unit. The first resonant unit is configured to transmit an input signal as a first wireless signal. The second resonant unit is configured to transmit the input signal as a second wireless signal. The first resonant unit and the second resonant unit have a substantially identical operating band, and the first resonant unit and the second resonant unit are a single continuous metal structure.

Abstract: An amplifier circuit is provided. The amplifier circuit outputs a pair of differential output signals through a first output terminal and a second output terminal. The amplifier circuit includes a first amplifier stage electrically connected to a first node and a second node for amplifying a pair of differential input signals; a second amplifier stage which is electrically connected to the first node and the second node and coupled to the first output terminal and the second output terminal; a first switch, coupled between the first output terminal and a first reference voltage; a second switch, coupled between the second output terminal and the first reference voltage; a third switch, coupled between the first node and the first reference voltage; a fourth switch coupled between the second node and the first reference voltage; and a fifth switch coupled between a second reference voltage and the first amplifier stage.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

Abstract: An inductor device includes a first trace, a second trace, a first capacitor, and at least one connection element. The first trace includes at least two sub-traces. One terminal of the at least two sub-traces is coupled to a first node. The second trace includes at least two sub-traces. One terminal of the at least two sub-traces is coupled to a second node. The first capacitor is coupled between the first node and the second node. The at least one connection element is coupled to another terminal of the at least two sub-traces of the first trace and another terminal of the at least two sub-traces of the second trace, such that the first trace and the second trace form a closed loop.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.