Abstract: A capacitor structure, including a transistor structure, a first metal conductive structure and a second metal conductive structure, is provided. The transistor structure includes a first ladder-shaped frame of a polycrystalline silicon layer and multiple first metal strips of a first metal layer. The first ladder-shaped frame is electrically isolated from the multiple first metal strips, and encircles a part of the multiple first metal strips. The first ladder-shaped frame forms a gate of the transistor structure. The multiple first metal strips form a drain and a source of the transistor structure. The first metal conductive structure is substantially overlapped with the first ladder-shaped frame. The second metal conductive structure is electrically connected to the multiple first metal strips, in which the second metal conductive structure is disposed across and electrically isolated from the first ladder-shaped frame and the first metal conductive structure.

Abstract: An analysis method configured to analyze original signals on an auxiliary channel of DisplayPort between a transmitter and at least one receiver, includes: receiving a first original signal of the original signals; dividing the first original signal to obtain a DPCD address and a first data; storing the first data according to the DPCD address; determining whether the first data is a redundant signal; when the first data is not the redundant signal, analyzing the first data; and displaying a topology of the at least one receiver. The operation of analyzing the first data includes generating the topology of the at least one receiver.

Abstract: The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal.

Abstract: An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit.

Abstract: The application discloses a circuit, including: a positive-terminal p-type transistor; a negative-terminal p-type transistor; a positive-terminal n-type transistor, wherein the positive-terminal p-type transistor and the positive-terminal n-type transistor are cascoded between a first reference voltage and a second reference voltage; a negative-terminal n-type transistor, wherein the negative-terminal p-type transistor and the negative-terminal n-type transistor are cascoded between the first reference voltage and the second reference voltage; a first positive-terminal capacitor, a top plate of the first positive-terminal capacitor is coupled to a gate of the positive-terminal n-type transistor; a first negative-terminal capacitor, a top plate of the first negative-terminal capacitor is coupled to a gate of the negative-terminal n-type transistor; a first control circuit, arranged to generate a first control signal to bottom plates of the first positive-terminal capacitor and the first negative-terminal capac

Abstract: A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of character images respectively corresponds to a plurality of characters of a character encoding format. The computing circuit is coupled with the first memory, and is configured to receive first update data generated by encoding input data according to the character encoding format, and is configured to use the first update data to update text data in a second memory. When the computing circuit reads the text data in the second memory, the computing circuit is configured to: search among the plurality of character images to find a plurality of target images corresponding to the text data; and output first display data according to the plurality of target images, in which the first display data is for generating a first display picture including the plurality of target images.

Abstract: A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

Abstract: An inductor structure includes a first connecting component, a second connecting component, and a center-tap terminal. In the inductor structure, a first port of the first connecting component is coupled to a first wire, and a second port of the first connecting component is coupled to a second wire. The second connecting component disposed above or beneath the first connecting component in an interlaced manner. The center-tap terminal is coupled to one of the first connecting component and the second connecting component. The center-tap terminal is disposed on a layer that is different from the layer where the first connecting component is disposed or the layer where the second connecting component is disposed.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit.

Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes a first and a second sub-trace. The first sub-trace includes first wires, and the second sub-trace includes second wires. The second sub-trace is coupled to the first sub-trace at a first node. The first and the second wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The second trace includes a third and a fourth sub-trace. The third sub-trace includes third wires, and the fourth sub-trace includes fourth wires. The fourth sub-trace is coupled to the third sub-trace at a second node. The third and the fourth wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The capacitor is coupled between the first and the second node.

Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes a first sub-trace and a second sub-trace. The first sub-trace and the second sub-trace form a plurality of first wires together at a first side of the inductor device, and form a plurality of second wires together at a second side of the inductor device. The second sub-trace is coupled to one terminal of the first sub-trace at a first node. The third sub-trace and the fourth sub-trace form a plurality of third wires together at the first side of the inductor device, and form a plurality of fourth wires together at the second side of the inductor device. The fourth sub-trace is coupled to one terminal of the third sub-trace at a second node. The capacitor is coupled to the first node and the second node.

Abstract: An inductor device includes a first wire, a second wire, a third wire, a fourth wire and an 8-shaped inductor structure. The first wire is disposed in a first area. The second wire is disposed in a second area. The third wire is disposed in the first area and at least partially overlapped with the first wire in a vertical direction. The third wire includes at least two third sub-wires, and the at least two third sub-wires are arranged with an interval between each other. The fourth wire is at least partially overlapped with the second wire in the vertical direction. The fourth wire includes at least two fourth sub-wires, and the at least two fourth sub-wires are arranged with an interval between each other. The eight-shaped inductor structure is disposed on an outer side of the third wire and the fourth wire.

Abstract: An LED driver includes an operational amplifier (OP), N current driving circuits, and a resistor circuit. The OP compares a reference voltage with a feedback voltage to generate a control voltage. Each current driving circuit is coupled with an LED, and includes: an NMOS transistor including a drain, a source, and a gate, and being turned on according to the control voltage in an enablement mode and turned off according to the voltage of a ground terminal in a disablement mode, wherein the drain is coupled with the LED and the voltage at the source is the feedback voltage; and a switch circuit coupling the OP with the gate in the enablement mode, and coupling the ground terminal with the gate in the disablement mode. The resistor circuit is coupled between the source and the ground terminal and controls the current passing through the N current driving circuits.

Abstract: The present invention discloses an image enlarging method having super resolution enlarging mechanism that includes the steps outlined below. An enlarging module of a neural network system receives an input image to generate an enlarged image. A front end convolutional path included in a neural network module of the neural network system receives the input image to perform convolution to generate a front end operation output result. Branching convolutional paths included in the neural network module respectively receive the front end operation output result to perform convolution to generate groups of output image residues. A mixing module of the neural network system weights the output image residues according to weighing settings related to image regions of the input image and mixes the weighted output image residues to generate a group of final output image residue such that an enhancement module enhances the enlarged image to generate an output enlarged image.

Abstract: An ambient light cancellation circuit functions as a Kth-order filter to filter out an ambient light signal of the detection signal, wherein the K is not fewer than two. The circuit includes a capacitive transimpedance amplifying circuit including an amplifier, a capacitor circuit, and a switch circuit. The capacitor circuit includes one or more capacitive paths coupled in parallel. The switch circuit couples the amplifier with the capacitor circuit in a non-cross manner or a cross manner. The non-cross manner is applied N times to let the capacitor circuit sample the detection signal N times while the detection signal includes a controllable-light signal and the ambient light signal; and the cross manner is applied M times to let the capacitor circuit sample the inversion of the detection signal M times while the detection signal includes the ambient light signal without the controllable-light signal, wherein (N+M) equals (K+1).

Abstract: A wireless transceiver having an in-phase quadrature-phase (IQ) calibration function includes a transmitter, a receiver, a signal generator, and a switch circuit. The switch circuit includes a first and a second switch circuits. The first switch circuit is turned on in a receiver-end calibration process, and outputs a predetermined signal from the signal generator to the transmitter. The second switch circuit is turned on in the receiver calibration process and outputs a derivative signal of the predetermined signal from the transmitter to the receiver to let the receiver performs a receiver-end IQ calibration accordingly. The first switch circuit is turned off and the second switch circuit is turned on in a transmitter-end calibration process; the second switch circuit outputs a radio-frequency signal from the transmitter to the receiver to let the receiver generates a calibration reference accordingly; and the transmitter performs a transmitter-end IQ calibration according to the calibration reference.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients.

Abstract: A comparator-based switched-capacitor circuit has a first output terminal and a second output terminal, and includes a switch-capacitor network, a first current source, and a second current source. Each of the first current source and the second current source includes a first transistor, a second transistor, a capacitor, and a buffer circuit. The first transistor has a first source, a first drain, and a first gate. The first drain is coupled to the first output terminal, the first source is coupled to a reference voltage, and the first gate is coupled to the switch-capacitor network. The second transistor has a second source, a second drain, and a second gate. The second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit is coupled between the second source and the second drain.

Abstract: A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.