Abstract: An electronic device includes a first circuit module and a second circuit module, wherein the first circuit module includes a write pointer generation circuit and a write data generation circuit for generating a write pointer and a write data; and the second circuit module includes a storage unit, a read pointer generation circuit and a comparator. The storage unit is used for storing the write data, the read pointer generation circuit is used for generating a read pointer, the comparator compares the write pointer and the read pointer to determine whether to read the write data from the storage unit, the write pointer and the write data are sent to the second circuit module through multiple wires, and a signal propagation time of the multiple wires is greater than one cycle of a clock signal used by the first circuit module.

Abstract: A multilane transmitter includes a plurality of transmitter lane circuits and a phase lock circuit. The phase lock circuit includes an oscillating circuit. The oscillating circuit is configured to provide clock signals corresponding to the transmitter lane circuits. The oscillating circuit includes a plurality of logic units. Clock receiving terminals of the transmitter lane circuits are coupled to an output terminal of one of the plurality of logic units.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device is arranged to operably transmit a corresponding first device information to the Bluetooth host device. The second member device is arranged to operably transmit a corresponding second device information to the Bluetooth host device. The Bluetooth host device is arranged to operably control a display device to simultaneously display a first device item for representing the first member device and a second device item for representing the second member device in a graphical user interface. The Bluetooth host device is further arranged to operably establish a Bluetooth connection with the first member device and conduct pairing procedure with the first member device after receiving a selection command corresponding to the first member device.

Abstract: A movie detection system and a movie detection method are provided. The method includes: capturing a current image of an input video source; performing a pre-processing process and an image scaling on the current image, cutting and retaining a top and a bottom of the current image, and joining the top and bottom to generate a joined current image; inputting the joined current image into a trained machine learning model to classify the joined current image as a movie image or a non-movie image. The trained machine learning model is generated by performing a training process on a machine learning model, and the training process is performed based on a plurality of joined training images. The joined training images are generated by performing the pre-processing process on a plurality of movie images with black bars and a plurality of non-movie images without black bars.

Abstract: An inductor device includes a first inductor, a second inductor, and at least one switch circuit. The second inductor is arranged to enclose the first inductor, and use a topmost layer metal to resist external interference for the first inductor. The at least one switch circuit is coupled to the second inductor, and is arranged to receive at least one control voltage, wherein the at least one control voltage is arranged to adjust conduction degree of the at least one switch circuit.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device transmits a device information of the first member device to the Bluetooth host device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device further establishes a connection with the first member device to conduct pairing procedure to generate a first cypher key after receiving a selection command. The first member device further establishes a connection with the Bluetooth host device to conduct pairing procedure to generate a second cypher key.

Abstract: A method for packet filtering in a network switch includes: utilizing an access control list circuit to filter received packets, wherein the access control list circuit compares header information of the received packets with an access control list to filter the received packets, where the access control list has at least one entry, and rule information in the entry includes only a portion of an IP address; and utilizing a routing circuit to further filter packets that pass the access control list circuit, wherein the routing circuit compares header information of the packets that pass the access control list circuit with a routing table to filter the packets, wherein the routing table has at least one entry, and rule information in the entry includes an entire IP address.

Abstract: A coordinate generation system, a coordinate generation method, a computer readable recording medium with stored program, and a non-transitory computer program product are provided. The coordinate generation system includes processing units and a neural network module. The processing units are configured to obtain four vertex coordinates of an image. The vertex coordinates include first components and second components. The processing unit is configured to perform the following steps: obtaining first vector based on the first components of the four vertex coordinates and repeatedly concatenating the first vector so as to obtain a first input; obtaining second vector based on the second components of the four vertex coordinates and repeatedly concatenating the second vector so as to obtain a second input; and obtaining first output coordinate components and second output coordinate components of output coordinates based on the first input, the second input, and parameters of the neural network module.

Abstract: A code checking method includes: causing a compiler to generate a map file and a low-level code file(s) according to a high-level code file(s); obtaining target function information from the map file; finding a target code file from the low-level code file(s); obtaining a first return command of a target function name of the target function information from the target code file; traversing the low-level code file(s) to obtain each calling module name and a second return command of each calling function name; obtaining a second storage area of each calling module name from the map file; and generating a check failure result when calling of a target function name by each calling function name is not complied with a bank-switching compile form according to a first storage area of the target function information, the first return command, each second storage area, and each second return command.

Abstract: A super resolution (SR) image generation circuit includes an image scale-up circuit, a stable SR processing circuit, a generative adversarial network (GAN) processing circuit, and a configurable basic block pool circuit. The image scale-up circuit is arranged to receive and process an input image to generate a scaled-up image. The stable SR processing circuit is arranged to receive a feature map of the input image to generate a stable delta value. The GAN processing circuit is arranged to receive the feature map to generate a GAN delta value. The configurable basic block pool circuit is arranged to dynamically configure a plurality of basic blocks according to a depth requirement of the input image, to generate a configuration result. The SR image generation circuit generates an SR image according to the scaled-up image, the stable delta value, and the GAN delta value.

Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

Abstract: A frequency mixing circuit includes: a first transistor and a second transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal of the first transistor is configured to receive an oscillation signal, the first terminal of the first transistor is configured to output a mixed signal, and the second terminal of the first transistor is configured to receive a source signal. The second transistor has a control terminal, a first terminal and a second terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor, the first terminal of the second transistor is coupled to the first terminal of the first transistor, and the second terminal of the second transistor is coupled to the control terminal of the first transistor.

Abstract: A method for data transmission and a data-processing circuit are provided. The data-processing circuit includes a memory that implements a buffer and a controller for controlling an operation of the data-processing circuit. When the data-processing circuit receives input data, data-hot-bits are used to address multiple data blocks of the input data. After analyzing the data-hot-bits, a starting address and a data length of each of the data blocks can be obtained. The input data is written to the buffer according to information analyzed from the data-hot-bits, and the data-hot-bits achieve an effect of masking the dummy data address. Further, data dependency among the data blocks can be confirmed by comparing the data-hot-bits with respect to each of the data blocks before the data blocks are written to the buffer.

Abstract: A method for matching parameters applied to a display device and a circuit system that performs the method are provided. In the method, when a display device is activated, a circuit system connects to a panel module of the display device for retrieving parameters from a panel memory. The parameters are such as video display parameters, camera image parameters, speaker audio parameters, and microphone receiving parameters. After the parameters are applied to the circuit system, the circuit system operates the display device using the parameters. The data generated by the circuit system can be adjusted for matching new parameters. Afterwards, when the new parameters are applied to the circuit system, video and audio are outputted according to the matched parameters, and the camera and microphone in the panel module are also operated according to the matched parameters.

Abstract: A computing device includes: a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time; a first computing circuit, for computing a payload time according to a packet length and a packet rate; a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

Abstract: A radio frequency receiving circuit includes a first amplification circuit, an oscillation circuit, a frequency mixing and amplification circuit and a dividing circuit. The first amplification circuit is configured to amplify an input signal so as to generate an amplified input signal. The oscillation circuit is configured to provide a local oscillation signal. The frequency mixing and amplification circuit is configured to mix and amplify the amplified input signal according to the local oscillation signal. The dividing circuit is configured to form a dividing loop at a preset frequency for the amplified input signal according to the local oscillation signal when the dividing circuit is driven. A chip including the radio frequency receiving circuit and a main circuit is also provided. The main circuit is configured to drive the dividing circuit when the second input signal is determined to include a signal of the preset frequency.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: An integrated circuit includes a power-on reset (POR) circuit, a watchdog timer, a first AND gate and a power management control circuit. The POR circuit is used to receive an input voltage to generate a POR signal and generate a clock signal. The watchdog timer is used to generate a timeout signal according to the clock signal when the POR signal has an enabling voltage, the clock signal enabling generation of timeout pulses in the timeout signal at predetermined time intervals. The first AND gate including a first input terminal for receiving the POR signal; a second input terminal for receiving the timeout signal; and an output terminal for outputting a reset signal according to the POR signal and the timeout signal. The power management control circuit is used to reset an output current in response to a reset pulse in the reset signal.

Abstract: An all-digital duty cycle corrector and a method for correcting a duty cycle of an output clock are provided. The all-digital duty cycle corrector includes a duty cycle adjustment circuit, an asynchronous sampler, a counter and a correction control circuit. The duty cycle adjustment circuit performs duty cycle adjustment on an input clock to generate the output clock according to a digital control code. The asynchronous sampler performs asynchronous sampling on the output clock to generate N sampling results at N time points, respectively. The counter counts a number of first logic values among the N sampling results to generate a counting result. The correction control circuit compares the counting result with a reference value to generate a comparison result, and selectively adjusts the digital control code according to the comparison result, in order to correct the duty cycle of the output clock.