Abstract: The present invention relates to various methods of fabricating Planar Bragg Gratings (PBG) in a doped waveguide in a Planar Lightwave Circuit (PLC) device, suppressing unwanted parasitic grating effects during fabrication of the device. One approach to reduce parasitic gratings is to use a hard mask before the waveguide photolithography and etch, that results in a steeper sidewall angle that reduces or eliminates the parasitic grating effect. Another method of reducing parasitic grating effect is to deposit a layer of developable Bottom Anti Reflective Coating (BARC) prior to depositing the photo resist for waveguide etch. A third method of resisting parasitic gratings comprises using a planarizing undoped silica layer as a barrier layer on top of the core. During subsequent high temperature annealing germanium outdiffuses laterally into the cladding.