Abstract: A ramp generator for a constant on-time DC-DC converter, wherein the ramp generator is configured to reduce DC offset and smooth transitions between conduction modes. The ramp voltage generator includes a common voltage generator suitable for generating a common voltage; a first ramp voltage generation block suitable for generating a first ramp voltage responsive to a first switching signal and a control signal, wherein the first switching signal resets one or more valley points of the first ramp voltage to one or more valley points of the common voltage; and a second ramp voltage generation block suitable for generating a second ramp voltage responsive to a second switching signal, the first ramp voltage, and the control signal.
Type:
Grant
Filed:
July 9, 2021
Date of Patent:
May 9, 2023
Assignee:
Reed Semiconductor Corp.
Inventors:
Jiwei Fan, Yingqian Ma, Jingyuan Chen, Hal Chen, Jialun Du