Abstract: An apparatus and method for performing byte swapping using a direct memory access (DMA) controller is provided. In a computer system, a DMA controller for a peripheral component is coupled to system memory via a bus. The DMA controller receives a command pointer to initiate a memory access operation. The command pointer specifies the location of the first DMA command in a command list to be executed by the DMA controller. Each DMA command includes an address word giving the starting address and length word indicating the number of data words to be accessed in memory. Because the data stored in memory is double-word aligned, the two least significant bits of the length word are not needed to perform the memory access and are instead used to indicate any byte swapping that is to be performed on the data during the memory access. During a memory access, the DMA controller swaps the bytes in each double-word of data as specified by the two least significant bits of the length word.

Abstract: A circuit in a graphics processing subsystem receives pixel color values as input and concurrently provides both dithering and scale correction of the color values. Pixel color values are initially generated by the subsystem as 8-bit binary quantities, each having a maximum possible value of 255. However, the graphics processing subsystem utilizes a scale of 0 to 256 for processing color values. The correction function prevents a loss of pixel intensity that would otherwise result from representing 8-bit color values on a 0 to 256 scale.

Abstract: A method and apparatus for performing color space conversion using blend circuitry in a graphics/video adapter is provided. Blend circuitry which is capable of blending two color values and fog circuitry which is capable of adjusting color values based on a fog factor are used. A first stage of converting a color value from YC.sub.r C.sub.b (YUV) color space to RGB color space is performed using the fog circuitry, and a second stage of converting the color value from the YC.sub.r C.sub.b (YUV) color space to RGB color space is performed using the blend circuitry, resulting in the generation of a converted color value .

Abstract: A method and an apparatus for writing display data to and reading display data from a FIFO. In one embodiment of the present invention, a memory controller coupled to a memory is configured to retrieve display data from the memory and write the retrieved data to a FIFO. The memory controller retrieves the display data from the memory in response to a FIFO write signal received from an output display controller. The output display controller is further configured to generate a FIFO read signal which is received by the FIFO. In response to the FIFO read signal, display data entries are sequentially read from the FIFO and transferred to an output display. The present invention features a programmable memory circuit such as a register, configured to store the value pointing to a particular display data entry in the FIFO. When the particular display data entry is read, a subsequent FIFO write signal is issued to the memory controller.

Abstract: A pixel engine pipeline (including a "front-end" and a "back-end") communicates pixel information between a graphics processor, a pixel engine, a data cache, and system memory. The "front-end" (for reading requested data) includes a command queue for receiving graphics instructions from a graphics processor. Read requests in the command queue are stored in a read request queue. Extraction instructions corresponding to at least a portion of the read request are stored in an attribute queue. Control logic determines whether the requested data is located in a data cache. The read request is stored in a load request queue and the requested data is retrieved from system memory into a load data queue, if the requested data is not in the data cache. The control logic stores the requested data into a read data queue. The requested data is provided to a stage of the pixel engine from the read data queue in accordance with the extraction instructions.

Abstract: A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the data caching mechanism includes an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating.

Abstract: A system and method that avoids performance bottlenecks at the host processor while avoiding tearing of the displayed image. In one embodiment, the system is composed of the host processor, a first in first out (FIFO) buffer, a co-processor, multiple frame buffers, a display controller and a display. The host and the co-processor are configured to enable the host to selectively batch graphic commands to the co-processor. The small set of commands provides the flexibility to selectively batch commands and selectively synchronize the host processor to the co-processor.