Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: The present disclosure generally provides for a method of forming a FinFET with a silicon germanium (SiGe) stressor, in addition to a FinFET structure obtained from embodiments of the method. The method can include forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin.

Abstract: Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

Abstract: A liquid crystal display apparatus includes a signal generating circuit configured to generate a first control signal and a second control signal; and a differential amplifier. The differential amplifier includes: a first differential pair of transistors configured to receive a differential input signal; a first constant current source connected with said first differential pair of transistors; and a first switch connected in parallel with said first constant current source and configured to increase current which flows through said first differential pair of transistors, in response to said first control signal which is active for a first time period in a level transition of said differential input signal.

Abstract: There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Abstract: The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: To improve a quality of a combined signal obtained by maximum ratio combining performed when a transmission signal of OFDM system is diversity-received with a small computation amount or a small circuit size. In a receiving apparatus, a combining unit corrects, when combining a sub-carrier signal of each branch obtained by performing Fourier transform on a reception signal of each branch at a maximum ratio for each sub-carrier, a weighting coefficient of each branch according to a magnitude relation of an intensity of the reception signal of each branch before Fourier transform. Specifically, the combining unit corrects the weighting coefficient of each branch so as to weaken an influence of a transmission path response estimated for a sub-carrier signal of the branch in branches with smaller reception signal intensities.

Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.

Abstract: A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract: A processor system according to the present invention includes a storage unit, a control information area that stores an access prohibit flag capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit and a request for rewriting a copy register, a security PE that evaluates whether or not the request for rewriting the copy register is valid, the copy register that stores, when the access prohibit flag is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit that controls whether or not to allow access from the main PEa to the storage unit based on an output value from the copy register.

Abstract: The present invention provides a magnetoresistive effect element which performs writing by a novel method. In a state in which a current does not flow in a magnetization free layer MFR, the magnetization free layer MFR has a magnetic wall MW1 on the side of a magnetization fixed layer MFX1. A magnetic wall MW2 is moved to the magnetic wall MW1 side by causing current to flow from the formed side of the magnetic wall MW1. Thus, an electrical resistance RMTJ between a reference layer REF and the magnetization free layer MFR changes from a low state to a high state.

Abstract: In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads.

Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: The suppression of resin leakage is combined with the suppression of damage to the functional wiring area of a wiring board in forming an encapsulation resin. A method for manufacturing a semiconductor device includes the step of clamping a wiring board with a first mold and a second mold. The second mold includes: a flat portion contacting a wiring board; a recessed portion forming a cavity to form an encapsulation resin; and a projecting portion formed at a location spaced apart from the recessed portion on the flat portion, the projecting portion projecting on the first mold side, and extending along the first edge of the wiring board.