Abstract: A receiver (36; 43) that is built to receive a load modulated analog input signal (3) and built to output digital data (4) detected in the input signal (3), which receiver (36; 43) comprises: either a first in-phase correlator (38) and a second in-phase correlator (40) or a first quadrature-phase correlator (45) and a second quadrature-phase correlator (46), which first in-phase correlator (38) comprises: a first in-phase subcarrier mixer (23-1) and a first subtraction stage (39) built to subtract an output signal (28-2) of the second quadrature-phase subcarrier mixer (23-4) from an output signal (27-1) of the first in-phase subcarrier mixer (23-1) and an integrator (26) built to continuously integrate an output signal of the first subtraction stage (39) over time during an integration window to provide the output signal of the first in-phase correlator (38); which second in-phase correlator (40) comprises: a second in-phase subcarrier mixer (23-2) and an first addition stage (41) built to add an outpu

Abstract: Mobile device (1) for wireless communication with another device in the HF frequency area, which mobile device (1) comprises: a communication stage (3) with a communication unit (4) connected via a first matching unit with a first antenna to optimize for a load modulated communication with the other device; a charge stage (13) with a charge unit (14) connected via a second matching unit with a second antenna to optimize for wireless charging of a battery (2) of the mobile device (1), wherein that the first and second antennas are realized as only one single antenna (9) and that the communication stage (3) comprises a first switch stage (6) arranged in the path between the communication unit (4) and the single antenna (9) to connect or disconnect the communication unit (4) to/from the single antenna (9) and that the charge stage (13) comprises a second switch stage (16) arranged in the path between the charge unit (14) and the single antenna (9) to connect or disconnect the charge unit (14) to/from the single

Abstract: The present disclosure provides a method for supporting a connection between devices serving on different channels, and a device serving on a first channel and supporting connection with a counterpart device serving on a second channel different from the first channel. The device includes a transceiver and a processor configured to control the transceiver. The processor is configured to broadcast a first beacon frame over the first channel, to generate a second beacon frame including information on the first channel, and to broadcast the second beacon frame over the second channel.

Abstract: A pass-through device is provided. The device includes a contactless RFID interface circuit that exchanges payload data with an RFID device, a wired contact interface circuit with at least two contact pins for wires to connect the pass-through device with an application device, a volatile memory for temporary storing payload data and a non-volatile memory, a buffer management circuit to manage write operations of payload data received from the contactless RFID interface circuit into at least a first buffer and a second buffer in the volatile memory and to manage read operations of payload data stored in the first buffer and second buffer to be transmitted with the wired contact interface circuit to pass the payload data through without storage of payload data in the non-volatile memory.

Abstract: An input stage for a signal processing circuit, the input comprising: a first differential pair; and a second differential pair; wherein the first differential pair and the second differential pairs have opposing skews which controls a voltage offset of the input stage.

Abstract: A device built to process a wireless interface communication type application is provided. The device includes a host controller circuit built to process device applications, that use the wireless interface communication type application, and built to process a host driver that communicates wired based on a first interface protocol. The device further includes a wireless interface controller circuit built to process a wireless interface for the wireless interface communication type application and built to process a controller driver that communicates wired with the host controller circuit.

Abstract: A driver circuit for controlling a switching element is provided. The driver circuit (200) has a plurality of bootstrap capacitors (210) and a switching unit (211). Furthermore, the driver circuit (200) has a control unit (102) which is configured to control the switching unit (211) in dependence of a control signal (ActHS) to provide a parallel arrangement of the plurality of bootstrap capacitors (210) between a charging voltage (VDD) and a reference voltage, for charging the plurality of bootstrap capacitors (210) during a charging phase; and to provide a serial arrangement of the plurality of bootstrap capacitors (210) between the charging voltage (VDD) and a control port of the switching element (MHS), for controlling the switching element (MHS) during a control phase.

Abstract: A voltage converter configured to provide an output voltage, the voltage converter comprising: a first device, configured to measure an absolute voltage with respect to a reference voltage; and a second device, configured measure a relative voltage with respect to the absolute voltage; such that the output voltage is regulated using the measurements of the absolute voltage and the relative voltage.

Abstract: A system comprising a current sensor for sensing an average output current and/or an average input current of a circuit is presented. There is a first switch, the first switch being arranged to selectively couple a sensing node of the circuit to a first voltage, wherein the current sensor comprises a pulse density modulator configured to generate a pulse density modulated signal. The pulse density modulated signal is dependent on an average current flowing through the first switch. The current sensor is configured to sense the average output current and/or the average input current of the circuit using the pulse density modulated signal.

Abstract: The present document describes a switching regulator (100) configured to generate an output voltage (VOUT) based on an input voltage (VDD) using at least one power switch (101) and an inductor. The switching regulator (100) comprises a first control circuit (120, 130) configured to generate a first control signal (131) for turning off the power switch (101), in dependence of a level of the inductor current (104) through the inductor. Furthermore, the switching regulator (100) comprises a second control circuit (200) configured to generate a second control signal (212) for turning on the power switch (101), in dependence of a level of the output voltage (VOUT).

Abstract: A signal amplifier includes a modulator circuit, a power converter and a H-bridge circuit. The modulator circuit generates a first logic signal by comparing an input signal with a first waveform and generates a second logic signal by comparing the input signal with a second waveform. The power converter provides a first voltage and a second voltage. The H-bridge circuit has a first input terminal to receive the first voltage, a second input terminal to receive the second voltage and a pair of output terminals for providing an output modulated voltage to a load. The H-bridge circuit generates the output modulated voltage using a primary modulation when the second logic signal is in a first logic state and using a secondary modulation when the second logic signal is in a second logic state.

Abstract: An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360° divided by a first variable n, the first variable n being an integer that is greater than or equal to two.

Abstract: A driver stage configured to switch an output node between a high-side potential and a low-side potential. The driver stage includes a high-side switch arranged between the high-side potential and the output node, a low-side switch arranged between the output node and the low-side potential, and an intermediate circuit arranged between the output node and an intermediate potential, wherein the intermediate potential lies between the high-side potential and the low-side potential. Furthermore, the driver stage includes a control unit configured to operate the driver stage at least in a high-side phase, in a low-side phase and in an intermediate phase.

Abstract: A controller for a switching converter. The switching converter is configured to receive an input voltage and to generate an output voltage. The switching converter includes one or more power switches and one or more energy storage elements. The one or more energy storage elements includes a first energy storage element. The controller is configured to control the switching converter while operating in a first control mode during a first state, and control the switching converter while operating in a hysteretic control mode during a second state.

Abstract: The present document describes an ESD protection circuit (100) which is configured to provide ESD protection between a first rail at an operating potential (111) and a second rail at a reference potential (112). The ESD protection circuit (100) comprises a detection unit (120) which is configured to detect an ESD event between the first rail and the second rail. Furthermore, the ESD protection circuit (100) comprises a clamp unit (130) configured to provide a discharge path between the first rail and the second rail, in reaction to an ESD event detected by the detection unit (120), wherein the clamp unit (130) comprises a main bipolar junction transistor (107) which is cascoded with an additional bipolar junction transistor (108, 308, 408) for providing the discharge path.

Abstract: A driver circuit for controlling a switching element is provided. The driver circuit (200) has a plurality of bootstrap capacitors (210) and a switching unit (211). Furthermore, the driver circuit (200) has a control unit (102) which is configured to control the switching unit (211) in dependence of a control signal (ActHS) to provide a parallel arrangement of the plurality of bootstrap capacitors (210) between a charging voltage (VDD) and a reference voltage, for charging the plurality of bootstrap capacitors (210) during a charging phase; and to provide a serial arrangement of the plurality of bootstrap capacitors (210) between the charging voltage (VDD) and a control port of the switching element (MHS), for controlling the switching element (MHS) during a control phase.

Abstract: The present document describes a capacitor circuit (100) which comprises a capacitor element (124) that is arranged between an intermediate node (122) and a reference potential (111), and a switching element (121) which comprises a first terminal that is coupled to the intermediate node (122) and a second terminal that is coupled to the reference potential (111) during the ON state of the switching element (121). Furthermore, the capacitor circuit (100) comprises a control unit (110, 210) which is configured to cause a transition from the ON state to the OFF state of the switching element (121) at a switching time instant; and, within a bias interval that is prior to the switching time instant, to transfer an electrical charge to the intermediate node (122), which is adapted to at least partially compensate an electrical charge that is transferred to the intermediated node (122) during the transition from the ON state to the OFF state of the switching element (121).

Abstract: A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the digital LDO being synchronized to a clock signal and comprising a first digital to analog converter configured to generate a first DAC code signal, the output voltage being dependent the first DAC code signal, trigger state transitions of the first DAC code signal between states, and for at least a portion of the state transitions of the first DAC code signal, trigger each subsequent state transition after more clock cycles of the clock signal than for the preceding state transition.

Abstract: A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage comprising a comparison circuit configured to receive the reference voltage, receive a feedback voltage, the feedback voltage being dependent on the output voltage, compare the reference voltage and the feedback voltage, and generate an error signal that is dependent on the comparison between the reference voltage and the feedback voltage, a first digital to analog converter configured to be operable in a panic mode in which the first digital to analog converter is configured to receive the error signal, generate a first DAC code signal based on the error signal for a first time period, the output voltage being dependent on the first DAC code signal, and calculate a mean value of the generated first DAC code signal during at least a portion of the first time period, and set the first DAC code signal to the mean value as calculated, a panic circuit configured to detect when the feedback voltage exceeds a fi

Abstract: A current measurement system for a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the current measurement system comprising a current determination unit configured to receive the first DAC code signal, and generate an output current signal using the first DAC code signal.