Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: Inverter circuits are connected to a P electrode and an N electrode, and control the U, V and W phases, respectively, of a three-phase motor. The inverter circuits are connected to the three-phase motor through shunt resistors, respectively. The shunt resistors are connected to HVICs, respectively. The HVICs are connected to a counter circuit. The counter circuit is connected to a CPU. The CPU is connected to a clock transmitter and a gate drive circuit.

Abstract: A BTL amplifier has a resistance element connected to an output reference voltage input terminal of an inverting amplifier. For offset compensation of the BTL amplifier, a variable current source controller controls an input switching circuit to cause application of compensation input voltages sent from an internal reference voltage source to a first input terminal and a second input terminal. The variable current source controller also controls a variable current source in response to an output signal from a comparator to minimize an output offset voltage, whereby a current flowing through the resistance element is adjusted to control the voltage at the output reference voltage input terminal.

Abstract: An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of collectively applying an erase pulse to a limited region in the memory block. Thereby, the number of the erase pulses excessively applied to the memory cells, which passed verify, can be reduced as compared with a conventional structure so that the number of the memory cells to be subjected to over-erase recovery write decreases, and the total block erase time can be short.

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A transfer mold type power module (“TPM”) is provided with a projection at each of the four corners on its front main surface. The TPM is also provided a first screw hole at its center. A shielding plate is provided with a second crew hole in a position that corresponds to the first screw hole. A control substrate is provided with third screw holes in positions that correspond to the projections. The shielding plate and the TPM are joined by putting a first screw through the first and second screw holes and temporarily fastening the tip of the first screw by a temporary fastening member at the rear main surface of the TPM. The control substrate and the TPM are joined by second screws via the third screw holes.

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: In a driving device (20) for driving an IGBT (1), a current measuring portion (22) measures a main current amount flowing through the IGBT (1). When the main current amount measured by the current measuring portion (22) reaches a predetermined reference level, a protection circuit portion (23) limits the main current at the IGBT (1) to protect it. A temperature measuring portion (24) measures the temperature of the IGBT (1). The control portion (25) adjusts the aforementioned reference level based on the temperature of the IGBT (1) measured by the temperature measuring portion (24). A control portion (35) stores setting values of the reference level as data.

Abstract: A BTL amplifier has a resistance element connected to an output reference voltage input terminal of an inverting amplifier. For offset compensation of the BTL amplifier, a variable current source controller controls an input switching circuit to cause application of compensation input voltages sent from an internal reference voltage source to a first input terminal and a second input terminal. The variable current source controller also controls a variable current source in response to an output signal from a comparator to minimize an output offset voltage, whereby a current flowing through the resistance element is adjusted to control the voltage at the output reference voltage input terminal.

Abstract: A dummy circuit including a plurality of dummy cells is provided in correspondence to a predetermined number of word lines. When either one of corresponding word lines are selected, a dummy bit line equal in load to a normal bit line is driven using the plurality of dummy cells included in this dummy circuit. A potential of this dummy bit line is detected by a dummy sense amplifier, and a sense enable signal is generated. Therefore, it is possible to accurately detect a sense timing irrespectively of array architecture.