Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate.

Abstract: In a method of manufacturing a camera module having a CMOS image sensor, a semiconductor chip to serve as a light sensor is mounted on a optical-component-mounting face of a wiring substrate mother board and, after bonding wires are connected to the semiconductor chip, a lens barrel is joined to the wiring substrate mother board so as to cover the semiconductor chip. A position adjustment pin and a through hole are provided on the lens barrel and the wiring substrate mother board respectively outside a junction face between the lens barrel and the wiring substrate mother board to be used for adjusting the position of the lens barrel with respect to the wiring substrate mother board by inserting the position adjustment pin into the through hole.

Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.

Abstract: Extremely thin chips laminated to a non-ultraviolet ray curing type adhesive tape are peeled from the tape without giving rise to cracks and chippings. In a center portion of a suction block used for peeling off a chip laminated to a dicing tape, three blocks which push the dicing tape upwardly are incorporated. With respect to these blocks, inside the first block having a largest diameter, there is a second block having a diameter smaller than the diameter of the first block. Further, inside the second block, there is a third block having the smallest diameter. To peel off a chip by pushing a back surface of the dicing tape with the blocks, first of all, the three blocks are simultaneously pushed upwardly by a certain amount and, thereafter, the intermediate block and the inner block are further pushed upward, and, finally, the inner block is further pushed upward.

Abstract: Plural elements forming a high frequency device in one chip are provided by forming a resistor element and the lower electrode of a capacitor element from one identical polycrystal silicon film over a substrate; forming the gate electrode of a power MISFET, upper electrode of the capacitor element, gate electrode of an n-channel type MISFET and gate electrode of a p-channel type MISFET from an identical polycrystal silicon film different from the other polycrystal silicon film and a WSi film; forming a capacitor element having a wiring formed on a silicon oxide film deposited over the substrate as a lower electrode and a wiring formed on the silicon oxide film as the upper electrode in the region MIN; forming a spiral coil in a region IND using an aluminum alloy film identical with that deposited on a silicon oxide film; and forming a bonding pad in a region PAD.

Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.

Abstract: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a contact layer formed on the clad layer, an insulation film covering the side surfaces of the clad layer, and an electrode connected to the contact layer, wherein the insulation layer has an end portion in the ridge thickness direction located between the upper surface and the lower surface of the contact layer.

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract: A method of manufacture of a semiconductor device can speedily peel extremely thin chips which are laminated to an adhesive tape without generating cracks or chippings. In this regard, the head of a vibrator is brought into contact with a back surface of an adhesive tape to which a plurality of semiconductor chips are laminated. By applying longitudinal vibrations having a frequency of 1 kHz to 100 kHz and an amplitude of 1 ?m to 50 ?m, the chip is peeled from the adhesive tape. In applying the longitudinal vibrations to the adhesive tape, a tension in a horizontal direction is applied to the adhesive tape.

Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.

Abstract: A package for mounting a semiconductor device has a surface exposed to an atmosphere. The exposed surface is covered with a covering material such as a paint, a tape or a seal.

Abstract: In a memory module, reference potential connecting patterns are disposed on high frequency signal lines and/or on the extension lines extending from the terminal ends of the signal lines as well as a shield cover for covering semiconductor memory chips is disposed on the substrate, and the reference potential connecting patterns are connected to the shield cover through metal cover contact parts.

Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

Abstract: To arrange semiconductor parts such as chip resistors and the like between a BGA and a mounting substrate, an interposes is disposed between the BGA and the mounting substrate for mounting the BGA thereon. The interposer serves to maintain the distance between the mounting substrate and the BGA to be just as large as or larger than the thickness of the semiconductor parts and to electrically connect solder balls of the BGA and electrically conductive patterns of the mounting substrate. The semiconductor parts are mounted on the mounting substrate before fixing the BGA 22 to the interposer.

Abstract: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a contact layer formed on the clad layer, an insulation film covering the side surfaces of the clad layer, and an electrode connected to the contact layer, wherein the insulation layer has an end portion in the ridge thickness direction located between the upper surface and the lower surface of the contact layer.

Abstract: A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.

Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate.

Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.