Patents Assigned to Renesas Electroncis Corporation
  • Patent number: 10403380
    Abstract: A semiconductor device with an anti-fuse element includes a semiconductor substrate, a well region of a first conductivity type formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate through a gate insulating film, and source regions of a second conductivity type opposite to the first conductivity type formed within the well region at the both ends of the gate electrode. When writing in the fuse element, a first writing potential is applied to the gate electrode, a first reference potential is applied to the well region, an intermediate potential is supplied to the source regions, and the intermediate potential is lower than the first writing potential and higher than the first reference potential.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 3, 2019
    Assignee: RENESAS ELECTRONCIS CORPORATION
    Inventor: Hiromichi Takaoka
  • Patent number: 10262720
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 16, 2019
    Assignee: Renesas Electroncis Corporation
    Inventor: Koji Nii
  • Patent number: 10200640
    Abstract: An image sensor device includes a plurality of pixel cells arranged in a matrix in a pixel array, and a timing control circuit that controls read-out of pixel information from the plurality of pixel cells. Each of the plurality of pixel cells includes a photodiode, a transfer transistor provided between the photodiode and a floating diffusion, a node reset transistor provided between a power supply terminal and the floating diffusion, a read-out capacitor whose one end is connected to the power supply terminal, a capacitor reset transistor provided between another end of the read-out capacitor and the floating diffusion, an amplification transistor that amplifies a voltage generated based on electric charges accumulated in the floating diffusion, and a selection transistor provided between the amplification transistor and a read-out line.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 5, 2019
    Assignee: Renesas Electroncis Corporation
    Inventor: Osamu Nishikido