Patents Assigned to RENESAS ELECTRONCS CORPORATION
  • Publication number: 20110195566
    Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONCS CORPORATION
    Inventors: Takashi ISHIGAKI, Ryuta TSUCHIYA, Yusuke MORITA, Nobuyuki SUGII, Shinichiro KIMURA, Toshiaki IWAMATSU