Patents Assigned to Renesas Electronic Corporation
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Publication number: 20230056809Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.Type: ApplicationFiled: October 28, 2022Publication date: February 23, 2023Applicant: Renesas Electronics CorporationInventor: Takeshi Kawamura
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Patent number: 11580043Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.Type: GrantFiled: August 6, 2021Date of Patent: February 14, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sho Yamanaka, Toshiyuki Hiraki
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Patent number: 11573134Abstract: A semiconductor device includes a first temperature sensor module, a second temperature sensor module, a first temperature controller, and a second temperature controller. The first temperature sensor module includes a bandgap reference circuit that outputs a plurality of divided voltages, and a first conversion circuit that performs analog-to-digital conversion processing on one of the plurality of divided voltages to generate a first digital value. The second temperature sensor module includes a second conversion circuit that performs analog-to-digital conversion processing on the one of the plurality of divided voltages to generate a second digital value. The first temperature sensor controller converts the first digital value to a first temperature. The second temperature sensor controller converts the second digital value to a second temperature.Type: GrantFiled: November 18, 2019Date of Patent: February 7, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadashi Kameyama, Masanori Ikeda
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Patent number: 11575319Abstract: A DC-DC converter includes a high-side switch coupled between a first power supply and an output terminal, a low-side switch coupled between a second power supply and the output terminal, an inductor coupled to the output terminal, and a reverse current monitoring circuit that determines that a reverse current from the inductor to the output terminal occurs when the output terminal becomes a high voltage during a state in which the high-side switch and the low-side switch are in a dead time.Type: GrantFiled: December 30, 2020Date of Patent: February 7, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masayuki Ida, Yasuhiko Kokami, Hideyuki Tajima, Hiroyuki Inoue, Noboru Inomata
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Patent number: 11568908Abstract: A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.Type: GrantFiled: January 26, 2021Date of Patent: January 31, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shunya Nagata, Yoshikazu Saito, Takeshi Hashizume
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Patent number: 11568226Abstract: A processing system includes a receiving circuit 1 for receiving an input signal from an externally connected sensor, an expected signal generating circuit 4 for automatically generating a teaching signal for use in the learning circuit 5, a learning circuit 5 for calculating a weight value, a bias value, and the like of the neural network model to form an expected signal from the teaching signal generated by the expected signal generating circuit 4 and the signal from the receiving circuit 1, an inference circuit 2 for performing signal processing based on a learned model of the neural network model generated by the learning circuit 5, and a validity verification circuit 3? for performing similarity calculation between an output signal of the inference circuit 2 and an expected signal for comparison.Type: GrantFiled: December 10, 2019Date of Patent: January 31, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasushi Wakayama
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Patent number: 11569867Abstract: The power line communication device detects inverter noise from the voltage waveforms of the power line, and executes the output of the transmission signal in a period in which it is determined that the signal amplitude of the transmission signal in the transmission processing unit exceeds a predetermined value from the output amplitude of the inverter noise, and stops the output of the transmission signal in other periods.Type: GrantFiled: September 14, 2021Date of Patent: January 31, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kosuke Shibuya, Yoshitaka Shibuya
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Publication number: 20230022468Abstract: An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.Type: ApplicationFiled: June 27, 2022Publication date: January 26, 2023Applicant: Renesas Electronics Corporation.Inventor: Fukashi MORISHITA
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Patent number: 11562897Abstract: A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.Type: GrantFiled: July 7, 2021Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hideki Makiyama
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Patent number: 11562175Abstract: An abnormality detection apparatus including a feature extraction circuit configured to extract a feature point and a feature value of a first image, and a feature point and a feature value of a second image, a flow calculation circuit configured to calculate, based on the feature value of the first image, a first abnormality detection circuit configured to detect an abnormality in the first image based on a first optical flow, and to detect an abnormality in the second image based on a third optical flow, and a second abnormality detection circuit configured to detect an abnormality in the first or second image based on a result of a comparison between the second optical flow and a fourth optical flow.Type: GrantFiled: May 26, 2020Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuki Kajiwara, Kosuke Miyagawa, Masaki Nishibu, Kentaro Sasahara
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Patent number: 11562774Abstract: The semiconductor device 1 comprises a processor 2, a memory connected to the processor and a control circuit, and comprises an active operation mode and a standby operation mode. The memory comprises a normal mode and a RS mode lower power consumption than the normal mode. The memory comprises SRAMs 7_0 to 7_5 which includes a mode terminal RS_T supplied with mode instruction signals RS1_0 to RS1_5 specifying the normal mode or the RS mode, respectively. The control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_0 to 7_2 in transition period which the semiconductor device transitions from the standby operation mode to the active operation mode. And the control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_3 to 7_5 after transition to the active operation mode.Type: GrantFiled: April 15, 2021Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koichi Tanigawa, Takayoshi Shiraishi
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Patent number: 11562957Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.Type: GrantFiled: March 3, 2021Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba
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Patent number: 11563020Abstract: A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.Type: GrantFiled: July 18, 2019Date of Patent: January 24, 2023Assignee: Renesas Electronics CorporationInventor: Tadashi Yamaguchi
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Patent number: 11563111Abstract: A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.Type: GrantFiled: July 14, 2020Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Patent number: 11557370Abstract: A semiconductor device includes an external terminal, an input buffer having an input terminal connected to the external terminal, a voltage generating circuit configured to generate a test voltage supplied to the input terminal, and a control circuit configured to determine whether the input buffer is deteriorated based on the test voltage supplied to the input terminal and an output level of the input buffer responding to the test voltage.Type: GrantFiled: April 9, 2021Date of Patent: January 17, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke Katagiri, Terunori Kubo, Hirotsugu Nakamura
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Patent number: 11557648Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.Type: GrantFiled: December 8, 2020Date of Patent: January 17, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Yanagigawa, Katsumi Eikyu, Masami Sawada, Akihiro Shimomura, Kazuhisa Mori
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Patent number: 11558218Abstract: A semiconductor device capable of performing filter processing while suppressing an increase in processing time is provided. The semiconductor device includes a microcontroller. The microcontroller comprises a CPU, a memory and a CAN-controller. The memory stores software. The CPU executes the software stored in the memory. The CAN controller is configured to add label information to the message information. The CAN routing software stored in the memory implements a filtering function for performing a filter processing for determining whether or not to route the message information by using the label information.Type: GrantFiled: May 10, 2019Date of Patent: January 17, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tsuyoshi Okumura
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Patent number: 11552629Abstract: A semiconductor device includes a first transistor that flows a current to a load, a current generation circuit that outputs a current corresponding to a power consumption of the first transistor, a temperature sensor, a resistor-capacitor network coupled between the current generation circuit and the temperature sensor and an overheat detection circuit coupled to a connection point of the current generation circuit and the resistor-capacitor network, wherein the resistor-capacitor network comprises a resistor and a capacitor corresponding to a thermal resistance and a thermal capacitance between the first transistor and the temperature sensor.Type: GrantFiled: June 16, 2021Date of Patent: January 10, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroki Nagatomi, Makoto Tanaka
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Patent number: 11552469Abstract: To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.Type: GrantFiled: August 25, 2020Date of Patent: January 10, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Dai Kamimaru
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Patent number: 11551755Abstract: A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.Type: GrantFiled: May 12, 2021Date of Patent: January 10, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Makoto Yabuuchi