Patents Assigned to Renesas Electronics America
  • Patent number: 12388700
    Abstract: A correction circuit for correcting an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal, the correction circuit comprising a plurality of variable gain circuits configured to provide in-phase and quadrature signals having balanced amplitudes and balanced phases, wherein each variable gain circuit is configured to apply a gain to amplify, attenuate or to pass a signal.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: August 12, 2025
    Assignee: Renesas Electronics America Inc.
    Inventors: Morteza Abbasi, Arjun Kamath, Tumay Kanar
  • Publication number: 20250246922
    Abstract: Systems and methods for operating a power converter of a device are described. A controller of the power converter may determine a battery voltage of a battery of the device and determine whether the battery voltage meets a threshold voltage. Responsive to determining that the battery voltage meets the threshold voltage, the controller may cause the power converter to operate in a pass-through mode where the power converter provides a load voltage to a load that is equal to the battery voltage. Alternatively, responsive to determining that that battery voltage does not meet the threshold voltage, the controller may cause the power converter to operate in a switching mode where the power converter provides the load voltage that is equal to the threshold voltage. By using the pass-through mode when the battery voltage meets the threshold voltage, a battery life of the device may be conserved.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 31, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Sungkeun LIM, Yen-Mo CHEN, Dongwoo HAN, Seung Ryul MOON
  • Publication number: 20250246927
    Abstract: Apparatuses, devices, and methods for operating a battery charger are described. A semiconductor device can include a controller that can monitor at least one battery parameter of a battery connected to a secondary stage of a two-stage battery charger. The controller can determine a threshold voltage based on the at least one battery parameter. The controller can regulate a midpoint voltage at the threshold voltage. The midpoint voltage can be provided by a primary stage of the two-stage battery charger to the secondary stage of the two-stage battery charger. The controller can operate the secondary stage in a non-switching mode to directly provide the midpoint voltage regulated at the threshold voltage to the battery.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 31, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Sungkeun LIM, Mehul Dilip SHAH, Shahriar Jalal NIBIR, Yen-Mo CHEN
  • Patent number: 12374320
    Abstract: A system and method for authenticating sound verbalized or otherwise generated by a live source within a monitored setting for voice-controlled or sound-controlled automation of a responsive process. One or more classifiers each generate a decision value according to values of predetermined signal features extracted from a received digital stream, and a sound type classification is computed according to an aggregate score of a predetermined number of decision values. The actuation of the responsive process is authenticated when the system discriminately indicates the captured sound signals to be verbalized or generated by a live source. The responsive process is thereby suppressed when the sound is instead determined to be reproduced or otherwise previously transduced, for example by a transmission or recording.
    Type: Grant
    Filed: June 12, 2024
    Date of Patent: July 29, 2025
    Assignee: Renesas Electronics America, Inc.
    Inventor: Jeffrey Sieracki
  • Patent number: 12361707
    Abstract: Captured samples of a physical structure or other scene are mapped to a predetermined multi-dimensional coordinate space, and spatially-adjacent samples are organized into array cells representing subspaces thereof. Each cell is classified according to predetermined target-identifying criteria for the samples of the cell. A cluster of spatially-contiguous cells of common classification, peripherally bounded by cells of different classification, is constructed, and a boundary demarcation is defined from the peripheral contour of the cluster. The boundary demarcation is overlaid upon a visual display of the physical scene, thereby visually demarcating the boundaries of a detected target of interest.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: July 15, 2025
    Assignee: Renesas Electronics America, Inc.
    Inventor: Jeffrey Mark Sieracki
  • Publication number: 20250216327
    Abstract: An optical module component for a gas sensor may comprise a first housing portion and a second housing portion. The first housing portion and the second housing portion may be configured to be joined together and to form a substantially cylindrical optical cavity when joined together. The optical module component may further comprise: a first opening for receiving light from a light source; at least one second opening for passing light from the optical cavity to a detector; a first curved reflecting element configured to direct the light from the light source into the optical cavity; and a second curved reflecting element configured to direct the light from the optical cavity to the detector. In particular, optical axes of the first and second curved reflecting elements may be tilted with respect to a diametral plane of the optical cavity.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Mohammad Taghi FATHI, Thomas REICHEL
  • Publication number: 20250219864
    Abstract: Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.
    Type: Application
    Filed: November 15, 2023
    Publication date: July 3, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Leonid GOLDIN, Greg Anton ARMSTRONG
  • Publication number: 20250219645
    Abstract: Apparatuses, devices, and systems for time synchronization are described. A timing circuit can include an analog phase lock loop (APLL), a plurality of digital phase lock loops (DPLLs) and a plurality of fractional output dividers (FODs). The timing circuit can receive the plurality of reference clock signals. The timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. The timing circuit can apply at least one operand on the at least one fractional frequency offset signal. The timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Menno SPIJKER, Michael RUPERT, Veronique ALLARD, Ketsana SOUKSANH
  • Publication number: 20250209030
    Abstract: Apparatuses, devices, and systems for detecting open pins are described. A controller can control at least one power stage. The controller can include a first set of interface pins, a digital communication bus and a circuit configured to switch connections between a reference voltage and the first set of interface pins. The controller can read a pin status of the at least one power stage via the digital communication bus. The pin status can indicate whether the reference voltage is detected at a second set of interface pins of the at least one power stage. The controller can, based on the pin status, detect a presence or an absence of an open pin condition between the first set of interface pins and the second set of interface pins.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Bo WANG, Chun CHEUNG
  • Patent number: 12341692
    Abstract: A system including a controller and a plurality of power stages is described. The system can include a communication interface, the plurality of power stages, and a controller connected to the plurality of power stages through the communication interface. The controller can generate a data packet including a command encoding a task and an address identifying at least one power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages through the communication interface. Each power stage among the plurality of power stages can receive the data packet through the communication interface, compare the address in the data packet with an address assigned to the power stage, determine whether to perform the task based on a result of the comparison between the address in the data packet with an address assigned to the power stage.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: June 24, 2025
    Assignee: Renesas Electronics America Inc.
    Inventors: Robert Thomas Grisamore, Kiran Gonsalves, James Robert Toker
  • Publication number: 20250202251
    Abstract: A method for operating a battery charging circuit is generally described. The method comprises obtaining a fault condition value and determining that a fault condition is present. The method further comprises setting a freeze signal to a first value based on the determination that the fault condition is present and outputting the freeze signal to a loop control circuit that is configured to inhibit a correction of a battery input current based on the freeze signal. The method further comprises re-obtaining the fault condition value and determining that the fault condition is not present. The method further comprises setting the freeze signal to a second value based on the determination that the fault condition is not present and outputting the freeze signal to the loop control circuit. The loop control circuit is configured to enable a correction of the battery input current based on the freeze signal.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 19, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Marco SAUTTO, Giovanni FIGLIOZZI, Sercan IPEK, Marcin Kamil AUGUSTYNIAK
  • Publication number: 20250202341
    Abstract: Systems and methods for method for operating a switching converter are described. A controller can sense a load current associated with an output voltage of a power stage. The controller can, based on the sensed load current, define a gate voltage at one of a default voltage level and a modified voltage level. The gate voltage can be for driving the power stage.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 19, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Rahul RAMESH, Yen-Mo CHEN, Sungkeun LIM
  • Publication number: 20250202359
    Abstract: In an embodiment, a semiconductor device is disclosed that includes a bidirectional unipolar-bipolar DC-DC circuit. The bidirectional unipolar-bipolar DC-DC circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor is connected between a reference ground connection and a first connection of a coil. The second transistor is connected between a positive bipolar input/output connection and the first connection of the coil. The third transistor is connected between a second connection of the coil and a negative bipolar input/output connection. The fourth transistor is connected between the second connection of the coil and a unipolar voltage input/output connection. The bidirectional DC-DC circuit is configured to concurrently activate the second and third transistors to cause a current flow through the coil between the positive bipolar input/output connection and the negative bipolar input/output connection.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 19, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Marco SAUTTO, Gustavo James MEHAS, Filippo Maria NERI, Fabio di FAZIO
  • Publication number: 20250202364
    Abstract: Apparatuses, devices, and methods for operating a voltage converter are described. A semiconductor device can include a first switching circuit comprising four switches and a flying capacitor. The semiconductor device can further include a second switching circuit comprising two switches. The semiconductor device can further include an inductor connected between a first phase node of the first switching circuit to a second phase node of the second switching converter. The first switching circuit and the second switching circuit can be combined to implement a buck-boost voltage converter that performs voltage conversion in a first direction from the first phase node to the second phase node and in a second direction from the second phase node to the first phase node.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 19, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Shahriar Jalal NIBIR, Rahul RAMESH, Yen-Mo CHEN, Sungkeun LIM, Gary KIDWELL
  • Patent number: 12320680
    Abstract: A method for dynamic error compensation of a position sensor and a position sensor are disclosed. In the method, a calculated speed of a moving target for a current determined position is compared to a calculated running average of the speed of the moving target over a certain number of determined positions and if the calculated speed of the moving target for the current position is within a first window around the calculated running average of the speed of the moving target over the certain number of determined positions the dynamic angle error is not re-calculated for the current determined position, and/or if the calculated speed of the moving target for the current determined position exceeds a second window the previously calculated running average is deleted and the calculation of the running average of the speed of the moving target over a certain number of determined positions is restarted.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: June 3, 2025
    Assignee: Renesas Electronics America Inc.
    Inventor: Ruggero Leoncavallo
  • Publication number: 20250149970
    Abstract: Apparatuses, devices, and methods for operating a voltage converter are described. A semiconductor device can include a switching circuit and a controller. The switching circuit can include a plurality of switching elements. The controller can determine an operation mode of the switching circuit. In response to the operation mode indicating a two-level operation mode, the controller can program the switching circuit to operate as a two-level voltage converter. In response to the operation mode indicating a three-level operation mode, the controller can program the switching circuit to operate as a three-level converter.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: Renesas Electronics America Inc.
    Inventors: Kee Ho SHIN, Phillip Marc JOHNSON, Sungkeun LIM, Yen-Mo CHEN
  • Patent number: 12292851
    Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.
    Type: Grant
    Filed: February 14, 2024
    Date of Patent: May 6, 2025
    Assignee: Renesas Electronic America Inc.
    Inventors: Ahmad Nasser, Tobias Belitz
  • Patent number: 12289193
    Abstract: Systems and methods for demodulating a signal is described. A device can receive a modulated signal that encodes data. The device can sample a voltage of the modulated signal to generate a plurality of samples in digital domain. The device can determine in-phase data and quadrature data of the plurality of samples. The device can determine amplitude data and phase data based on the in-phase data and the quadrature data. The device can decode the amplitude data and phase data into digital symbols that represent the data encoded in the modulated signal.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: April 29, 2025
    Assignee: Renesas Electronics America Inc.
    Inventors: Damla Solmaz Acar, Mihail Jefremow, Jure Menart, Pooja Agrawal, Amit Bavisi, Gustavo James Mehas
  • Patent number: 12278558
    Abstract: Methods and systems for operating a voltage regulator are described. A integrated circuit can be configured to adjust at least one of a deadtime parameter and a drive strength parameter of a power stage based on at least one of an input voltage being provided to a power stage, a switch node voltage of the power stage, and an output current of the power stage. A controller of the power stage can be further configured to adjust a deadtime of the power stage based on adjustment of the deadtime parameter. The controller can be further configured to adjust a drive strength of the first driver and the second driver based on adjustment of the drive strength parameter.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: April 15, 2025
    Assignee: Renesas Electronics America Inc.
    Inventors: Chun Cheung, Ankit Sharma, Bo Wang
  • Patent number: 12276532
    Abstract: A method and a system may inductively determine a position of a display screen of a computing device. Associated processes may generate a magnetic field by providing an alternating current to a driver coil, and may generate a voltage at a sensor coil in response to the magnetic field. The system and method may additionally include determining a linear position of the display screen by executing an algorithm at a processor. An input to the algorithm may include voltage data associated with the voltage generated at the sensor coil. The linear position of the display screen may correspond to a size of the display screen between a minimum size and a maximum size.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 15, 2025
    Assignee: Renesas Electronics America Inc.
    Inventors: Gustavo James Mehas, Damla Acar, Ashley De Wolfe, Pooja Agrawal, Nicholaus Wayne Smith