Patents Assigned to RENESAS ELECTRONICS COPRORATION
  • Patent number: 10452587
    Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventors: Hiroshi Ueda, Seiji Mochizuki, Toshiyuki Kaya, Kenichi Iwata, Katsushige Matsubara
  • Patent number: 10032896
    Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventor: Hitoshi Matsuura
  • Patent number: 10002953
    Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 19, 2018
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventor: Nao Nagata