Abstract: An adaptive control system (2) for controlling a plant (3) is disclosed. The adaptive control system comprises a control system (5) configured to generate drive signals (16) for the plant in dependence upon a reference signal (8) and an error signal, and a state observer (17) or state sensor (17?; FIG. 2) configured to generate an estimate of a state of the plant in dependence upon the reference signal. The system comprises an error combiner (12) configured to selectably combine a first error (11) determined from the reference signal and a set of measurements of the plant and a second error (13) determined from the reference and the estimate.

Abstract: A fixed logic integrated circuit is disclosed. The integrated circuit comprises a unique code generator configured to generate a code having a value which is intrinsically unique to the integrated circuit, an enrolment pattern generator configured to generate an enrolment pattern based on the unique code. The integrated circuit is configured to transmit the enrolment pattern to an external enrolment device and to receive enabling data from the external enrolment device. Optionally, the integrated circuit may include memory for storing remotely-generated enabling data. The integrated circuit comprises a configuration file generator configured to generate configuration data using the remotely-generated enabling data and the unique code, and a feature activation module configured to activate and/or disable features of the integrated circuit and/or customise the integrated circuit in dependence upon the configuration data.

Abstract: A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m?1, and k*m memories, where k?2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories.

Abstract: A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).

Abstract: An integrated circuit is described. The integrated circuit comprises a one-time programmable non-volatile memory and a memory controller for the one-time programmable non-volatile memory. The memory controller is configured to send a first random number which has been generated in the integrated circuit to a device initialization server. The memory controller is configured, in response to receiving a signed device initialization message from the device initialization server, the signed device initialization message comprising a device initialization message and a corresponding signature, and the device initialization message comprising a second random number and a device identity, to determine whether the first and second random numbers are equal and whether the signature is valid.

Abstract: A device for allowing a CAN 2.0B controller to participate passively in CAN FD communication is described. The device is configured to identify whether a frame on RXD is a CAN FD frame and, in dependence upon identifying that the frame is a CAN FD frame, to replace a section of the CAN FD frame, including the data phase of the CAN FD frame, with substitute data having a format which complies with CAN 2.0B. The device may be included in a CAN transceiver.

Abstract: A digital-to-analog converter (DAC) is described. The DAC comprises a resistor having a resistance R and a capacitor having a capacitance C. The DAC comprises a first switching element configured, in response to a first control signal, to couple the capacitor to a first rail via a path having a resistance less than R and a second switching element configured, in response to a second control signal, to couple the capacitor to the first rail through the resistor. The DAC also comprises a third switching element configured, in response to a third control signal, to couple the capacitor to a second rail (8) via a path having a resistance less than R and a fourth switching element configured, in response to a responsive to a fourth control signal, to couple the capacitor to the second through the resistor. The capacitor can be quickly charged or discharged over a period less than RC or less than 0.7 RC.