Patents Assigned to Renesas Esatern Japan Semiconductor, Inc.
  • Patent number: 6989587
    Abstract: There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 24, 2006
    Assignees: Renesas Technology Corp., Renesas Esatern Japan Semiconductor, Inc.
    Inventors: Mamoru Ito, Akira Muto, Tomio Yamada, Tsuneo Endoh, Satoru Konishi, Kazuaki Uehara, Tsutomu Ida, Koji Odaira, Hirokazu Nakajima