Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: A replacement cell determining part is configured so as not to handle, as a cell that should be replaced, the case where the sole difference is the cell identification name and other data are matched, in addition to the case where all of the cell identification name, the cell type name, the pin name of the cell, and the signal name assigned to the pin are matched. A rerouting signal determining part is configured so as not to handle, as a signal that should be rerouted, the case where the sole difference is the signal name and other data are matched, in addition to the case where all of the signal name, the pin name to which the signal is applied, the cell identification name of a cell possessed by the pin, and the cell type name of the cell are matched.

Abstract: A free page extracting unit extracts a free page of a non-volatile memory. A directory page writing unit writes, to the free page extracted by the free page extracting unit, a directory that includes a logical page/physical page translation table of a page to which updated data are to be written. Further, a data page writing unit writes updated data to the free page extracted by the free page extracting unit. Therefore, even when data updating operation is interrupted, loss of the original data can be prevented, and the data before updating can be recovered.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: In a spread spectrum clock generator, a DLL circuit delays an oscillation clock signal from a VCO and outputs ten delay clock signals having different phases respectively. A selector selects any one of the ten delay clock signals, and outputs a selected clock signal. A control circuit controls a signal selection operation of the selector. A feedback frequency divider divides a frequency of the selected clock signal by a frequency division ratio N, and generates a comparison clock signal. In this manner, a phase of the comparison clock signal can be fine-tuned. Therefore, a spread spectrum clock generator capable of frequency modulation with high accuracy can be obtained.

Abstract: A layout design apparatus can develop a semiconductor integrated circuit in a shorter period at a lower cost. It includes an initial layout section for performing placement and routing using a netlist of the entire semiconductor integrated circuit such that a first circuit layout whose wiring consists of n (n≧2) wiring layers is formed in a first circuit region, and a second circuit layout, which has wiring consisting of (n−m) (m<n) wiring layers and is connected to the first circuit layout, is formed in a second circuit region; and a layout modifying section for performing placement and routing using a netlist of a third circuit to form a third circuit layout such that its wiring consists of the (n−m) wiring layers constituting the wiring of the second circuit, and for replacing the second circuit layout by the third circuit layout.

Abstract: An on-screen display unit includes OSD (on-screen display) RAMs each for storing data on one of OSD blocks to be subjected to OSD; a memory bus for transferring data to be stored to the OSD RAMs from a CPU; and an OSD local bus for transferring the data stored in the OSD RAMs to make the OSD. The OSD RAMs are supplied with the data to be stored through the control of switches alternately, and transfer the stored data to the OSD local bus 12 alternately. The on-screen display unit can cope with a high frequency OSD clock signal, and carry out the OSD normally.

Abstract: An information security microcomputer includes an encryption circuit encrypting and decrypting information, an authentication program authenticating an ICE main body, and a CPU performing entire control of the information security microcomputer. CPU stops at least a part of a function of the information security microcomputer when the ICE main body cannot be authenticated. Therefore, an unauthorized person cannot use the information security microcomputer as an ICE microcomputer so that security can be improved.

Abstract: A house code assigning device includes a communication unit for sending a command for requesting transmission of a house code to electronic equipment included in a system and for receiving a house code from the electronic equipment, a verification unit for verifying whether or not a house code received by the communication unit is correct and for outputting a verification result showing whether or not the house code received by the communication unit is correct, and a display control unit for controlling a light emitting unit according to the verification result from the verification unit.