Patents Assigned to Renesas Technology
  • Patent number: 7738845
    Abstract: The present invention provides electronic parts for amplifying high frequency power capable of expanding a dynamic range of an output power detection circuit, obtaining a continuous detection output having no inflexion point from a low region of output power to its high region and thereby improving controllability of the output power. In a wireless communication system which controls output power of a high frequency power amplifier, based on an output power detection signal and a signal indicative of an output level, an output power detection circuit is provided with a multi-stage configured amplifier which amplifies a high frequency signal taken out via a coupler and capacitive elements. Further, a plurality of detection circuits which detect outputs of amplifiers of respective stages, and a detection circuit which detects the high frequency signal without passing through the multi-stage configured amplifier are provided.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: June 15, 2010
    Assignees: Renesas Technology, Hitachi Hybrid Network Co., Ltd.
    Inventors: Kyoichi Takahashi, Nobuhiro Matsudaira, Takashi Yokoi
  • Patent number: 7403361
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: July 22, 2008
    Assignees: Renesas Technology, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Patent number: 7002826
    Abstract: A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0-WLAn connected to a first port 13a, and a plurality of second word lines WLB0-WLBn connected to a second port 13b. Each of a plurality of first word lines WLA0-WLAn and each of a plurality of second word lines WLB0-WLBn are arranged alternately in a planar layout. A semiconductor memory device is thus obtained that allows a coupling noise between interconnections to be reduced without an increase in memory cell area.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology
    Inventor: Koji Nii