Abstract: An apparatus and method of manufacture may be provided for a package that can be coupled to a common heat sink without external electrical isolation. The apparatus, for example, can include a semi-conductor die comprising at least one electronic device. The apparatus can also include a frame on which a bottom side of the die is mounted, a bottom side of the frame being configured to attach to a printed circuit board. The apparatus can further include a high thermal conductivity resin molded onto a top side of the die.

Abstract: A method can include obtaining a voltage across a first transistor as an obtained voltage. The method can also include multiplying the obtained voltage by a predetermined multiple M to yield a multiplied voltage. The method can further include applying the multiplied voltage to a second transistor, wherein the second transistor is N times smaller than the first transistor. The method can additionally include providing an output current of the second transistor as an M/N scaled estimate of an output current of the first transistor.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: An apparatus, in one embodiment, can include a configuration including a plurality of heat generation devices. The apparatus also includes a plurality of thermal sensors respectively, operably connected to each of the plurality of heat generation devices, wherein each thermal sensor of the plurality of thermal sensors includes a respective output terminal configured to provide a voltage representative of the temperature of the respective heat generation device. The apparatus further includes an output circuit configured to output the highest temperature information among the heat generation devices. The output terminals of the plurality of thermal sensors are tied together. A corresponding method is also discussed.

Abstract: Methods and apparatus for sharing network bandwidth between devices connected to a bus are presented. Each of the devices belongs to one of a number of device classes. Each device class is associated with a respective data transfer rate at which information may be exchanged over the bus. An exemplary method includes the step of assigning a gap interval to each device based on at least the data transfer rate of the class to which the device belongs, the assigned gap interval being inserted between portions of a data stream sent by the corresponding device over the bus. The assigned gap interval may be inserted between portions of a data stream sent by the corresponding device over the bus to achieve the desired data rate resulting in an equitable sharing of bandwidth between the devices connected to the bus.

Abstract: A DC motor comprises a stator having at least three windings coupled to a neutral point; a first pair of upper and lower switches for driving a first winding of the at least three windings to a first voltage or in tristate; a second pair of upper and lower switches for driving a second winding of the at least three windings to a second voltage or in tristate; a third pair of upper and lower switches for driving a third winding of the at least three windings to a third voltage or in tristate, one of the first, second or third windings being in tristate; a back electro-motive force (BEMF) signal generation circuit coupled to receive a BEMF voltage from the winding in tristate; a comparator coupled to receive the BEMF voltage and a zero-crossing voltage representing the voltage at the neutral point at a predetermined time and for comparing the BEMF voltage and the zero-crossing voltage to generate a comparison result; a zero-crossing voltage generation circuit to output the zero-crossing voltage to the comparato

Abstract: Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong “on” state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: Embodiments of a current sensing circuit for a multi-phase DC-DC converter are disclosed. In one embodiment, an integrated circuit (IC) may be provided that has high- and low-side switch arrays being coupled to an output terminal as well as being coupled between high and low voltage terminals. The switch arrays may also include at least one bonding pad and at least one bonding wire. The IC may also include a driver coupled to the switch arrays for driving the switch arrays and a sensing circuit that coupled to the bonding pad for detecting a signal passing through the bonding wire.

Abstract: Methods and arrangements for configuring a functional network of devices are presented. The devices are addressable within a logical network operable on a shared physical bus. According to an exemplary method, a configuration session is established between at least one controlling device and at least one controlled device operable within the logical network. The at least one controlling and controlled devices enter respective time-limited configuration modes for an overlapping period of time to establish the configuration session. Linkage transaction messages are exchanged between the at least one controlled and controlling devices during the configuration session. Configuration information included in the linkage transaction messages is stored in memory of the respective at least one controlled and controlling devices during the configuration session.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: Enhanced functionality is provided in memory devices by enhancing the control logic to recognize predetermined data sequences. Standard (legacy) device operations are used to communicate the predetermined data sequences, thereby allowing existing device drivers to be used with the enhanced devices.

Abstract: Enhanced functionality is provided in memory devices by enhancing the control logic to recognize predetermined data sequences. Standard (legacy) device operations are used to communicate the predetermined data sequences, thereby allowing existing device drivers to be used with the enhanced devices.

Abstract: Magneto-resistive (MR) head pre-amplifiers for single polarity power supply applications are presented. An exemplary pre-amplifier includes a bias network coupled to first and second input terminals of the pre-amplifier, the input terminals for receiving signals corresponding to variations in magnetic fields from an MR head. At least one gain stage having first and second input terminals and first and second output terminals for amplifying the received signals is included. A pair of coupling capacitors, each capacitor being connected between a respective input terminal of the pre-amplifier and a corresponding respective input terminal of the at least one gain stage, are further included in the pre-amplifier design. Finally, the exemplary pre-amplifier includes a pair of feedback capacitors, each capacitor being connected between respective input and output terminals of the at least one gain stage. The pre-amplifier is powered by a single polarity power supply.

Abstract: A method for storing memory test information includes the steps of storing a portion of information related to locations and numbers of failed memory cells detected while testing memory, and updating the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable. The first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.

Abstract: A method and apparatus are described for adaptively removing interference from a signal. A received signal is amplified linearly along a first signal path to provide a first signal and amplified nonlinearly along a second signal path to provide a second signal. The received signal propagates through the first and second signal paths at substantially the same time. The first and second amplified signals are mixed in proportion according to determined first and second weights, respectively, to provide an output signal having interference removed. The output signal is filtered to produce a first filtered signal corresponding to a ripple envelope of the output signal and filtered substantially simultaneously to produce a second filtered signal corresponding to an average peak detected value of the output signal. The first and second filtered signals are compared to produce an error signal. The first and second weights are determined according to the error signal.

Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Abstract: In a system having multiple analog circuits that share a common power supply, where a change in the operational state of one circuit can have an effect on the performance of another circuit, a determination is made when any one of the circuits enters a state where its performance could be affected. Under such a condition, the other circuits that share the common power supply are placed in a state where their effect on the operation of the first circuit will be negligible. This state for the other circuits can be one of maximum current draw, so that subsequent operation by the other circuits will not alter the demands on the power supply.

Abstract: Methods and apparatus for feature recognition time shift correlation are presented. An exemplary method includes the step of identifying a feature in an input data stream. A starting time associated with the identified feature relative to a boundary of the input data stream is stored. A time interval until the identified feature is next repeated in the input data stream is then measured. Next, the measured time interval is compared to each of a set of valid interval values for the identified feature. A difference is then calculated between the stored starting time and a starting time associated with the identified feature relative to a boundary of a reference data sequence when the measured time interval matches one of the valid interval values. The calculated difference determines an amount that the input data stream must be time-shifted to achieve correlation with the reference data sequence.

Abstract: A method and system are described for monitoring a deliverable radio frequency (RF) power of an amplifier operable on a monolithic microwave integrated circuit (MMIC). According to an exemplary embodiment, circuitry is configured to capture, on the MMIC, a first portion of an RF signal transmitted from the amplifier to a load, and a second portion of the RF signal reflected from the load back to the amplifier. Circuitry is also configured to generate, on the MMIC, a first signal proportional to an RF power of the first portion of the RF signal, and a second signal proportional to an RF power of the second portion of the RF signal. Additional circuitry is configured to subtract a first reference signal from the first signal to produce a third signal, and a second reference signal from the second signal to produce a fourth signal. Finally, circuitry is configured to subtract the fourth signal from the third signal to produce an output signal proportional to the deliverable RF power of the amplifier to the load.