Abstract: A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: There have been provided a semiconductor device capable of preventing defects associated with etching, such as an increase in leak current, deterioration in film-coating properties and deterioration in transistor properties, and a method for manufacturing the semiconductor device. A CMOS transistor includes, on the same semiconductor substrate, an NMOS transistor having a gate electrode and a PMOS transistor having a gate electrode, wherein the former gate electrode includes a gate insulating film, a polycrystal silicon layer, a metal layer and another polycrystal silicon layer, and the latter gate electrode includes a gate insulating film, a metal layer and a polycrystal silicon layer.

Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.

Abstract: There is provided a semiconductor device of which the circuit scale does not significantly increase even with an ECC function. A microcomputer having an internal flash memory inserts one weight in a sense amplifier activation signal only when an error detection signal is on the H level at a given time in a read cycle or when the error detection signal which was on the H level in a previous read cycle has shifted to the L level in a current read cycle. This allows the retrieval of output data signals after waiting till the output data signals through error correction are determined only when an error is contained in the output data signals.

Abstract: Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.

Abstract: A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outer

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: A first semiconductor chip, a spacer of plane shape, and a second semiconductor chip are put on a module substrate, sequentially. These semiconductor chips have a relation that every side of the first semiconductor chip is shorter than the first side and the second side of the second semiconductor chip, and longer than the third side and the fourth side of the second semiconductor chip. The border of the spacer is parallel to the third side and the fourth side and is placed inside the border of the first semiconductor chip. Even if the second electrode pad of the second semiconductor chip approaches the border of the first semiconductor chip, since a spacer secures space between the border portion of the first semiconductor chip and the second semiconductor chip, the wire combined with the second electrode pad does not contact the first semiconductor chip.

Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

Abstract: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded.

Abstract: An electrically rewritable non-volatile memory device is configured by the EEPROM 3, and an electrically non-rewritable non-volatile memory device is configured by the OTPROM 4a. Both the EEPROM 3 and the OTPROM 4a are configured by phase change memory devices each of which can be fabricated in the same fabrication step and at a low cost. The EEPROM3 uses a phase change memory device in which an amorphous state and a crystal state of a phase change material are used for memory information, while the OTPROM 4a uses a phase change memory device in which a non-disconnection state and a disconnection state of a phase change material are used for memory information.

Abstract: To provide a power supply unit capable of realizing a multiphase power supply at low cost. For example, each of a plurality of semiconductor devices DEV[1]-DEV[n] comprises a trigger input terminal TRG_IN, a trigger output terminal TRG_OUT, and a timer circuit TM that delays a pulse signal input from TRG_IN and outputs it to TRG_OUT. DEV[1]-DEV[n] are mutually coupled in a ring shape by its own TRG_IN being coupled to TRG_OUT of one semiconductor device other than itself. Each of DEV[1]-DEV[n] performs switching operation by using the pulse signal from TRG_IN as a starting point, and feeds a current into an inductor L corresponding to itself. Moreover, DEV[1] generates the above-described pulse signal only once during startup by a start trigger terminal ST being set to a ground voltage GND, for example.

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.

Abstract: After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.