Patents Assigned to Renesas Technologyy Corp.
  • Patent number: 6754865
    Abstract: N-bit external data input from the outside is converted to m-bit data (m>n) by simultaneous write circuits and the m-bit data is supplied to a semiconductor memory. When m-bit data is read out of the semiconductor memory, coincidence judgement results are output. Thus, in a memory-logic-combined integrated circuit, the semiconductor memory can be efficiently tested without a lot of external data input/output terminals.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: June 22, 2004
    Assignee: Renesas Technologyy Corp.
    Inventor: Yoshiyuki Haraguchi