Patents Assigned to RENESAS TECHNONOLY CORP.
  • Publication number: 20080050864
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Application
    Filed: October 18, 2007
    Publication date: February 28, 2008
    Applicant: RENESAS TECHNONOLY CORP.
    Inventors: Shigenobu MAEDA, Toshiaki IWAMATSU, Takashi IPPOSHI