Abstract: Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder.

Abstract: There is provided a technology to realize high speed data transfer while compatibility of a card type storage device comprising a nonvolatile memory is ensured. Namely, in the card type storage device comprising the nonvolatile memory, a plurality of data terminals are provided and an interface unit is provided with a circuit for determining levels of data terminals. Some or all of the plurality of data terminals are connected with pull-up resistors for pulling up to a power source voltage. When the determination circuit determines that the data terminals connected with the pull-up resistors are in an open condition, the determination circuit switches a bus width (number of bits) of data.

Abstract: A receiver of a communication device includes: a differential amplification circuit; two capacitors for applying only the amplitude components of two input clock signals complementary to each other to the gates of two N-channel MOS transistors of the differential amplification circuit; and an initialization circuit for applying a predetermined reference potential to the gates of the two N-channel MOS transistors in a non data communication state. Thus, it is possible to make a quick and stable transition from a non data communication state to a data communication state.

Abstract: An AlCu alloy interconnect line (100) including a TiN barrier layer (110), a lower Ti metal layer (120), an AlCu layer (130) and a TiN cap layer (140) is formed on a plasma oxide film formed on a semiconductor substrate in which devices are formed. Heat treatment is conducted to cause Al contained in the AlCu layer (130) and Ti contained in the lower Ti metal layer (120) to react with each other, thereby forming a lower AlTi alloy layer (150) in a lower portion of the AlCu layer (130). A via hole (170) is thereafter formed. A current path extending from the via hole (170) to reach the lower AlTi alloy layer (150) is ensured without passing through the AlCu layer (130), allowing electromigration resistance to be improved.

Abstract: A wafer production management device includes: a process flow definition table storing for each type of wafer a production flow and a masking level applied in a production process; a basic production information table storing a mask set's name for each type of wafer; a mask information definition table storing for each mask set a plurality of masks' names correlated with a masking level; a lot information table storing a production flow and a type of wafer for each production lot; a processing portion selecting from the basic production information table a mask set's name corresponding to a type of wafer stored for each production lot; a processing portion extracting a masking level based on the current step and the process flow definition table; and a processing portion driven by the mask set's name and the masking level to select a mask's name from the mask information definition table.

Abstract: An electromagnetic field analyzer (11) finally replaces a fill metal pattern in a wiring pattern library (32) with an insulator of high dielectric constant, and stores, in a capacitance value data base (33), parasitic capacitance value information in which values of parasitic capacitances parasiting the insulator and fill metal patterns are in correspondence. A regression analyzer (12) stores, in a regression equation data base (36), regression equation information for deriving parasitic capacitance values from the fill metal patterns and associated size information. A parasitic capacitance extractor (13) obtains values of parasitic capacitances parasiting the replacing insulator for outputting parasitic capacitance information (37) while applying a regression equation of the regression equation information to the size information associated with the fill metal patterns.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card.

Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

Abstract: A power amplifier system having a high frequency power amplifier circuit section 10 employing as its amplifying elements source-grounded enhancement type n-channel MESFETs J1, J2 for receiving a drain bias voltage Vdd and a gate bias voltage Vgg of zero volts or positive low potentials as supplied from a unipolar power supply and for amplifying an input signal superposed therewith to thereby output an amplified signal indicative of a change in drain currents Id1, Id2, an output matching circuit section 11 for applying impedance matching to such amplified high frequency signal and then outputting the resultant signal, and a gate bias voltage circuit section 12 for supplying a gate bias voltage to the high frequency power amplifier circuit is disclosed along with a mobile communications terminal device including the system, wherein the MESFETs J1, J2 are such that in cases where a forward direct current (DC) gate voltage is applied to a gate terminal with a source terminal coupled to the ground, the DC gate vol

Abstract: A memory cell part of a semiconductor substrate is formed with a cylindrical capacitor opening extending perpendicularly to the main surface of the semiconductor substrate. The cylindrical capacitor opening passes through a silicon oxide film, a silicon nitride film and another silicon oxide film in this order. A capacitor lower electrode, a dielectric film and a capacitor upper electrode are formed in the cylindrical capacitor opening along the surface of the cylindrical capacitor opening. The bottom surface of the cylindrical capacitor opening is formed below the main surface of silicon nitride film. Thus obtained is a semiconductor device capable of improving refreshability and soft error resistance.

Abstract: A memory bank comprises nonvolatile memory sections and two buffer sections to respectively store information of access unit of the nonvolatile memory sections. In response to the instruction of access operation, the memory bank performs data transfer between one buffer section of the memory bank and the nonvolatile memory section. In parallel to this data transfer, the memory bank also enables control of interleave operation to perform data transfer between the other buffer section of the relevant memory bank and the external side. Accordingly, high speed access can be realized by conducting in parallel the data transfer between the nonvolatile memory section and the buffer section and data transfer between the buffer section and the external side in the interleave operation. Moreover, high speed write and read access to the nonvolatile memory section can also be realized.

Abstract: Ions are implanted into a resist pattern for forming a wiring pattern. Argon is employed as the ion species, for performing ion implantation under 50 keV at 1×1016/cm2. Due to the ion implantation, the thickness of the resist pattern contracts to about 334 nm, i.e., about 75% of the thickness of 445 nm before ion implantation, while the composition of the resist pattern changes for improving resistance against etching for a silicon nitride film and a polysilicon layer. Thus obtained is a method of manufacturing a semiconductor device capable of suppressing critical dimension shift density difference (difference between a critical dimension shift on a rough region having a relatively large space width and that on a dense region having a relatively small space width).

Abstract: A detection circuit in a semiconductor memory device includes a first latch circuit and a second latch circuit. The first latch circuit latches a data strobe signal at a rise of a clock signal after a write latency passes. The second latch circuit receives an output signal of the first latch circuit at a rise of a clock signal to output a detection signal. Circuits in the semiconductor memory device are controlled by a detection signal. With such an operation applied, the semiconductor memory device grasps a correct phase difference between a data strobe signal and a clock signal, thereby enabling a normal operation.

Abstract: A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.

Abstract: An analog switch and an analog multiplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.

Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

Abstract: Provided are a semiconductor device comprising a polymetal gate electrode that can prevent formation of a silicide layer at the interface between metal and conductive silicon and also exhibit low resistance property and ohmic property, and a method for manufacturing the same. Specifically, a polymetal gate electrode is formed via a gate insulating film (2), e.g., an oxide film, on a semiconductor substrate (1), e.g., a silicon substrate. The polymetal gate electrode has such a structure that a conductive silicon film (3), e.g., a poly-Si film, a silicide film (4), e.g., a WSi film, a barrier film (5), e.g., a WSiN film, and a metal film (6), e.g., a W film, are stacked over the semiconductor substrate (1) in the order named.

Abstract: A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.

Abstract: A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.