Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid-state device where a solid-state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid-state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid-state device side connection member.

Abstract: A solid-state image sensor device comprises an image sensor section for outputting analog signals of an image being taken; a plurality of AD converter sections, arranged with respect to the column direction of the image sensor section, for converting the analog signals into digital signals; a drive circuit section for controlling the image sensor section and the AD converter sections; and a plurality of differential interface sections for transmitting the digital signals converted by the AD converter sections as differential output signals to an external device. Each of the differential interface sections comprises a current value changeover circuit and offset voltage holding circuit operative when an operation mode changeover is made.

Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid state device where a solid state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid state device side connection member.

Abstract: A method for measuring a shape of a phase defect existing on an exposure mask includes making inspection light incident on the mask, measuring the intensity of light scattered in an angular range in which the width of an scattering area on the phase defect can be predicted, calculating a radius of the phase defect based on the measured scattered light intensity, changing the angular range of scattered light to be measured, remeasuring scattered light intensity in the thus changed angular range, and calculating a scattering cross-sectional area based on the scattered light intensity obtained by remeasurement. A process of remeasuring the scattered light intensity and calculating the scattering cross-sectional area is repeatedly performed until the remeasured scattered light intensity is saturated and the shape of the phase defect is determined by using the calculated radius of the phase defect and each of the calculated scattering cross-sectional areas.

Abstract: An authenticating system according to the present invention has a characteristic structure of which an authenticating section 32 of a note type PC 10 and an authenticating section 42 of a battery 20 are directly connected through I/O ports 51 and 61, respectively. Thus, the authenticating system according to the present invention can be relatively easily accomplished using a conventional system. The present invention can be applied to a system that is composed of a plurality of electronic devices that perform an authenticating process.

Abstract: A reflection-type exposure mask includes a multilayer reflective film in a main surface and serving as a high reflective region to an exposure light, and an absorber pattern on the multilayer reflective film and serving as a low reflective region to the exposure light, wherein a phase difference between reflection lights of the exposure light from the multilayer reflective film and the absorber pattern is in a range of 180°±10°, and the absorber pattern includes first and second linear patterns having longitudinal directions intersecting at right angles, contrast values of optical images of the first and second linear patterns formed on a wafer is to be 0.6 or more when one of the longitudinal directions of the first and second patterns agree with an incident direction of the exposure light to the main surface viewed from above the main surface.

Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal.

Abstract: The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove.

Abstract: A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A reflective-type mask having a main surface including a pattern region in the main surface, the pattern region including a multilayer reflective film which reflects the exposure light and a first absorber pattern on the multilayer reflective film, the first absorber pattern including a pattern which absorbs the exposure light and corresponds to a pattern to be formed on a wafer, a light shielding region in the main surface for preventing a region on the wafer excluding a predetermined region from being irradiated with the exposure light when the main surface is irradiated with the exposure light for transferring the first absorber pattern to the predetermined region, the light shielding region including a second absorber pattern having a lower reflectivity to the exposure light than the first absorber pattern and being provided in a position differing from a position in which the first absorber pattern is provided.

Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: In a reception apparatus, a matched filter that has conventionally been arranged in a searcher unit is mounted on an acquisition unit together with a large scale memory. The large scale memory once stores reception chip signals, and thereafter outputs them to the matched filter and to the delay profile calculation unit. A setting register receives an acquisition signal and outputs it to the matched filter. The matched filter performs acquisition of the reception chip signals outputted from the large scale memory, and outputs a despread timing signal to a despread circuit, a code generation circuit and the delay profile calculation unit.

Abstract: A method of determining defects in photomasks according to the present invention is designed to increase the yield of the manufacture of photomasks and to decrease the cost of inspecting the photomasks. In the method, circuit data 1 representing a circuit to be formed on a semiconductor substrate by photolithography is prepared, and layout data 2 is prepared from the circuit data 1. The layout data is converted to compensated layout data by performing RET. Further, mask-manufacturing data is developed from the compensated layout data. To form patterns on a semiconductor substrate by photolithography, attribute information is imparted to the mask-manufacturing data. The attribute information represents whether the patterns are adaptive to electrically active regions or electrically non-active region. In the mask-inspecting process 6, a criterion for determining whether the patterns formed on the photomasks have defects is changed in accordance with the attribute information.

Abstract: A semiconductor device capable of reducing power consumption is provided. When a power to an internal circuit is interrupted, e.g., in a standby mode, a switch is turned off, and a pseudo-ground line is charged with a leak current of the internal circuit to raise a potential thereof. After the switch is turned off, a switch connected to a charge supply unit is turned on while the potential is rising, so that the charge supply unit is electrically coupled to the pseudo-ground line. Thereby, charges accumulated in the charge supply unit are discharged to the pseudo-ground line. The switch is turned off to decouple electrically the charge supply unit from the pseudo-ground line. Thereby, when the power supply is interrupted, a part of the charges for raising the potential of the pseudo-ground line is supplemented with the charges of the charge supply unit.

Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.