Patents Assigned to Reniac, Inc.
  • Patent number: 11126600
    Abstract: A system and method for accelerating compaction includes a compaction accelerator. The accelerator includes a compactor separate from a processor performing read and write operations for a database or a data store. The compactor is configured to receive a table to be compacted and entries written in the table, each of the entries being associated with a timestamp indicating when they were respectively written; identify, using a plurality of sort engines operating in parallel, the entries that were written last based on the timestamps; mark, using a plurality of marker engines operating in parallel, older copies of the entries for deletion; create, using the plurality of marker engines, tombstones for the older copies; create a compacted table, including the entries that were last written; delete the tombstones and the entries associated with the tombstones; and generate a freemap based on storage locations of the entries associated with the tombstones.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 21, 2021
    Assignee: RENIAC, INC.
    Inventors: Chidamber Kulkarni, Prasanna Sundararajan
  • Patent number: 11044314
    Abstract: A database proxy includes a request processor, a cache, a database plugin, and interfaces for coupling the database proxy client devices, other database proxies, and database servers. The request processor is configured to receive a read request from a client, determine whether the read request is assigned to the database proxy, and return results of the read request to the client. When the read request is not assigned to the database proxy, the read request is forwarded to another database proxy. When the read request is assigned to the database proxy, the read request is processed using data stored in the cache when the results are stored in the cache or forwarded to the database plugin, which forwards the read request to a database server, receives the results from the database server, and returns the results to the request processor for storage in the cache.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 22, 2021
    Assignee: RENIAC, INC.
    Inventors: Chidamber Kulkarni, Aditya Alurkar, Pradeep Mishra, Prasanna Sukumar, Vijaya Raghava, Raushan Raj, Rahul Sachdev, Gurshaant Singh Malik, Ajit Mathew, Prasanna Sundararajan
  • Patent number: 10931587
    Abstract: A system includes a field-programmable gate array (FPGA) with a configurable logic module. The configurable logic module is configured to implement a protocol endpoint, the protocol endpoint including a congestion control module. In some examples, the protocol endpoint corresponds to a transport control protocol (TCP) endpoint. In some examples, state information associated with a networking protocol implemented by the protocol endpoint is stored in and retrieved from block memory of the configurable logic module. In some examples, no state information associated with the networking protocol is stored in and retrieved from a memory other than the block memory. In further examples, the congestion control module is configured to perform operations comprising monitoring a congestion condition of a network and dynamically switching among a plurality of congestion control algorithms based on the monitored congestion condition.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 23, 2021
    Assignee: RENIAC, INC.
    Inventors: Chidamber Kulkarni, Prasanna Sundararajan
  • Patent number: 10237350
    Abstract: A database proxy includes a request processor, a cache, a database plugin, and interfaces for coupling the database proxy client devices, other database proxies, and database servers. The request processor is configured to receive a read request from a client, determine whether the read request is assigned to the database proxy, and return results of the read request to the client. When the read request is not assigned to the database proxy, the read request is forwarded to another database proxy. When the read request is assigned to the database proxy, the read request is processed using data stored in the cache when the results are stored in the cache or forwarded to the database plugin, which forwards the read request to a database server, receives the results from the database server, and returns the results to the request processor for storage in the cache.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: March 19, 2019
    Assignee: RENIAC, INC.
    Inventors: Chidamber Kulkarni, Aditya Alurkar, Pradeep Mishra, Prasanna Sukumar, Vijaya Raghava, Raushan Raj, Rahul Sachdev, Gurshaant Singh Malik, Ajit Mathew, Prasanna Sundararajan
  • Publication number: 20180307711
    Abstract: A system and method for accelerating compaction includes a compaction accelerator. The accelerator includes a compactor separate from a processor performing read and write operations for a database or a data store. The compactor is configured to receive a table to be compacted and entries written in the table, each of the entries being associated with a timestamp indicating when they were respectively written; identify, using a plurality of sort engines operating in parallel, the entries that were written last based on the timestamps; mark, using a plurality of marker engines operating in parallel, older copies of the entries for deletion; create, using the plurality of marker engines, tombstones for the older copies; create a compacted table, including the entries that were last written; delete the tombstones and the entries associated with the tombstones; and generate a freemap based on storage locations of the entries associated with the tombstones.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 25, 2018
    Applicant: RENIAC, INC.
    Inventors: Chidamber Kulkarni, Prasanna Sundarajan
  • Patent number: 10049035
    Abstract: A disclosed stream memory management circuit includes a first memory controller circuit for accessing a first memory of a first type. A second memory controller circuit is provided for accessing a second memory of a second type different from the first type. An access circuit is coupled to the first and second memory controller circuits for inputting and outputting streaming data. An allocation circuit is coupled to the access circuit, the allocation circuit configured and arranged to select either the first memory or the second memory for allocation of storage for the streaming data in response to attributes associated with the streaming data. A de-allocation circuit is coupled to the access circuit for de-allocating storage assigned to the streaming data from the first and second memories.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 14, 2018
    Assignee: Reniac, Inc.
    Inventors: Chidamber Kulkarni, Prasanna Sundararajan
  • Patent number: 9286221
    Abstract: A heterogeneous memory system includes a main memory arrangement, a first-level cache, a second-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and the second-level cache includes a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the first-level cache or the second-level cache for storage of the first data and stores the first data in the selected one of the first or second-level caches. The MMU reads second data from one of the first-level cache or second-level cache and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: March 15, 2016
    Assignee: Reniac, Inc.
    Inventors: Prasanna Sundararajan, Chidamber Kulkarni
  • Patent number: 9262325
    Abstract: A heterogeneous memory system includes a network interface card, a main memory arrangement, a first-level cache, and a memory management unit (MMU). The main memory arrangement, first-level cache and the MMU are disposed on the network interface card. The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: February 16, 2016
    Assignee: Reniac, Inc.
    Inventors: Prasanna Sundararajan, Chidamber Kulkarni