Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.

Abstract: The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

Abstract: A semiconductor device includes a trench isolating elements, a memory cell transistor and a peripheral circuit Vcc transistor having a thermal oxide film of a first thickness, and a peripheral circuit Vpp transistor including a thermal oxide film and a thermal oxide film formed before trench formation, having a second thickness greater than the first thickness.